MCP6273T-E/SN Microchip Technology, MCP6273T-E/SN Datasheet - Page 13

• Manufacturer Part Number: MCP6273T-E/SN
• Description: IC OPAMP 2.0V SNGL CS R-R 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP6273T-E/SN

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Slew Rate: 0.9 V/µs
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 3000µV
• Current - Supply: 170µA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -

4.0
The MCP6271/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low cost, low power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
make the MCP6271/1R/2/3/4/5 ideal for battery
powered applications.
4.1
4.1.1
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages.
exceeding both supplies with no phase inversion.
4.1.2
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors, and to minimize input bias
current (I
when they try to go more than one diode drop below
V
above V
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1:
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute Maxi-
mum Ratings † at the beginning of Section 1.0 “Elec-
trical
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V
and V
resistors R
of the input pins. Diodes D
pins (V
© 2008 Microchip Technology Inc.
SS
. They also clamp any voltages that go too far
V
V
V
IN
IN
DD
IN
SS
Characteristics”).
–) from going too far below ground, and the
+
DD
+ and V
APPLICATION INFORMATION
Rail-to-Rail Inputs
B
). The input ESD diodes clamp the inputs
Figure
1
; their breakdown voltage is high enough to
Figure 2-34
Bond
Bond
Bond
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
Pad
Pad
Pad
and R
IN
4-1. This structure was chosen to
2
–) from going too far above V
limit the possible current drawn out
Simplified Analog Input ESD
Stage
Input
shows
1
and D
Figure 4-2
an
2
prevent the input
Bond
Pad
input
shows
V
IN
DD
voltage
–
, and
the
IN
+
dump any currents onto V
shown, resistors R
through D
FIGURE 4-2:
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
the diodes D
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
V
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
Figure
need to limit the usable voltage range.
4.1.3
The input stage of the MCP6271/1R/2/3/4/5 op amps
uses two differential CMOS input stages in parallel.
One operates at low common mode input voltage (V
and the other at high V
operates with V
(see
age (V
V
The transition between the two input stage occurs
when V
6). For the best distortion and gain linearity, with non-
inverting gains, avoid this region of operation.
4.2
The output voltage range of the MCP6271/1R/2/3/4/5
op amps is V
(maximum) when R
and V
tion.
IN
DD
MCP6271/1R/2/3/4/5
V
V
–) should be very small.
1
2
+ 0.3V to ensure proper operation.
Figure 2-7
DD
2-32. Applications that are high impedance may
CM
OS
Rail-to-Rail Output
= 5.5V. Refer to
R
R
1
1
) is measured at V
1
2
≈ V
R
R
and D
and R
NORMAL OPERATIONS
1
>
>
1
2
D
DD
and D
DD
1
V
V
and
SS
SS
CM
– 15 mV (minimum) and V
D
2
– 1.1V (see
2
2
CM
.
. In this case, the currents through
– (minimum expected V
– (minimum expected V
up to 0.3V past either supply rail
1
2
Figure
L
) is below ground (V
need to be limited by some other
= 10 kΩ is connected to V
and R
Protecting the Analog
CM
MCP627X
Figure 2-17
. With this topology, the input
DD
2 mA
2 mA
2-10). The input offset volt-
V
2
R
. When implemented as
Figure 2-3
DD
3
also limit the current
CM
= V
DS21810F-page 13
for more informa-
SS
and
– 0.3V and
SS
1
2
)
)
SS
Figure 2-
V
+ 15 mV
IN
OUT
); see
+ and
DD
CM
/2