MCP6142-E/MS Microchip Technology, MCP6142-E/MS Datasheet - Page 15

• Manufacturer Part Number: MCP6142-E/MS
• Description: IC OPAMP 1.4V DUAL R-R 8MSOP
• Manufacturer: Microchip Technology

Specifications of MCP6142-E/MS

• Slew Rate: 0.003 V/µs
• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 100kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 3000µV
• Current - Supply: 0.6µA
• Current - Output / Channel: 20mA
• Voltage - Supply, Single/dual (±): 1.4 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Op Amp Type: Rail To Rail
• No. Of Amplifiers: 2
• Bandwidth: 100kHz
• Supply Voltage Range: 1.4V To 6V
• Amplifier Case Style: MSOP
• No. Of Pins: 8
• Number Of Channels: 2
• Voltage Gain Db: 115 dB
• Common Mode Rejection Ratio (min): 60 dB
• Input Offset Voltage: 3 mV
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Details

4.0
The MCP6141/2/3/4 family of op amps is manufactured
using Microchip’s state of the art CMOS process These
op amps are stable for gains of 10 V/V and higher. They
are suitable for a wide range of general purpose, low
power applications.
See Microchip’s related MCP6041/2/3/4 family of op
amps for applications needing unity gain stability.
4.1
4.1.1
The MCP6141/2/3/4 op amps are designed to not
exhibit phase inversion when the input pins exceed the
supply voltages.
exceeding both supplies with no phase inversion.
4.1.2
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors, and to minimize input bias
current (I
when they try to go more than one diode drop below
V
above V
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1:
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute
Maximum Ratings † at the beginning of Section 1.0
“Electrical Characteristics”).
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V
and V
resistors R
of the input pins. Diodes D
pins (V
© 2009 Microchip Technology Inc.
SS
. They also clamp any voltages that go too far
V
V
V
IN
IN
DD
IN
SS
–) from going too far below ground, and the
+
DD
+ and V
APPLICATIONS INFORMATION
Rail-to-Rail Input
B
). The input ESD diodes clamp the inputs
Figure
1
; their breakdown voltage is high enough to
Bond
Bond
Bond
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
Pad
Pad
Pad
and R
IN
Figure 2-10
4-1. This structure was chosen to
2
–) from going too far above V
limit the possible current drawn out
Simplified Analog Input ESD
Stage
Input
1
and D
shows an input voltage
Figure 4-2
2
prevent the input
Bond
Pad
shows the
V
IN
DD
–
, and
IN
+
dump any currents onto V
shown, resistors R
through D
FIGURE 4-2:
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
the diodes D
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
V
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
Figure
need to limit the usable voltage range.
4.1.3
The input stage of the MCP6141/2/3/4 op amps uses
two differential input stages in parallel. One operates at
a low common mode input voltage (V
other operates at a high V
device operates with a V
and 300 mV below V
measured at V
ensure proper operation.
There are two transitions in input behavior as V
changed. The first occurs, when V
V
V
best distortion performance with non-inverting gains,
avoid these regions of operation.
IN
SS
DD
–) should be very small.
+ 0.4V, and the second occurs when V
V
V
– 0.5V (see
1
2
2-33. Applications that are high impedance may
R
R
1
1
1
2
and D
and R
NORMAL OPERATION
1
R
R
>
>
and D
D
1
2
V
V
MCP6141/2/3/4
1
SS
SS
CM
2
Figure 2-3
2
D
CM
.
. In this case, the currents through
– (minimum expected V
– (minimum expected V
2
= V
1
2
) is below ground (V
need to be limited by some other
SS
and R
Protecting the Analog
SS
. The input offset voltage is
CM
– 0.3V and V
MCP604X
DD
2 mA
2 mA
CM
up to 300 mV above V
and
2
. When implemented as
. With this topology, the
V
also limit the current
DD
Figure
DS21668D-page 15
CM
DD
2-6). For the
CM
), while the
1
2
CM
)
)
V
+ 0.3V to
SS
OUT
is near
IN
is near
); see
+ and
CM
DD
is