AD8130ARM Analog Devices Inc, AD8130ARM Datasheet - Page 9

IC AMP DIFF LN LDIST 40MA 8MSOP

AD8130ARM

Manufacturer Part Number
AD8130ARM
Description
IC AMP DIFF LN LDIST 40MA 8MSOP
Manufacturer
Analog Devices Inc
Type
Diff Receiverr
Datasheet

Specifications of AD8130ARM

Slew Rate
1100 V/µs
Mounting Type
Surface Mount
Rohs Status
RoHS non-compliant
Design Resources
High CMRR Circuit for Converting Wideband Complementary DAC Outputs to Single-Ended Without Precision Resistors (CN0142)
Amplifier Type
Differential
Number Of Circuits
1
-3db Bandwidth
290MHz
Current - Input Bias
500nA
Voltage - Input Offset
400µV
Current - Supply
13mA
Current - Output / Channel
40mA
Voltage - Supply, Single/dual (±)
4.5 V ~ 25.2 V, ±2.25 V ~ 12.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
No. Of Amplifiers
1
Bandwidth
270MHz
No. Of Pins
8
Settling Time
20ns
Operating Temperature Max
85°C
Peak Reflow Compatible (260 C)
No
Number Of Channels
1
Number Of Elements
1
Power Supply Requirement
Single/Dual
Common Mode Rejection Ratio
86dB
Voltage Gain Db
71dB
Unity Gain Bandwidth Product (typ)
110MHz
Input Resistance
6@5VMohm
Input Offset Voltage
1.8@5VmV
Input Bias Current
2@5VnA
Single Supply Voltage (typ)
5/9/12/15/18/24V
Dual Supply Voltage (typ)
±3/±5/±9/±12V
Rail/rail I/o Type
No
Single Supply Voltage (min)
4.5V
Single Supply Voltage (max)
25.2V
Dual Supply Voltage (min)
±2.25V
Dual Supply Voltage (max)
±12.6V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
8
Package Type
MSOP
Output Type
-
Gain Bandwidth Product
-
Lead Free Status / Rohs Status
Not Compliant

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ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Input Voltage (Any Input)
Differential Input Voltage (AD8129)
Differential Input Voltage (AD8129)
Differential Input Voltage (AD8130)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
specified for the device soldered in a circuit board in still air.
Table 5. Thermal Resistance
Package Type
8-Lead SOIC/4-Layer
8-Lead MSOP/4-Layer
Maximum Power Dissipation
The maximum safe power dissipation in the AD8129/AD8130
packages is limited by the associated rise in junction temp-
erature (T
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8129/AD8130.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in the silicon devices, potentially
causing failure.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
JA
V
V
is specified for the worst-case conditions, that is, θ
S
S
≥ ±11.5 V
< ±11.5 V
J
) on the die. At approximately 150°C, which is the
θ
121
142
JA
Rating
26.4 V
Refer to Figure 4
−V
±8.4 V
±0.5 V
±6.2 V
−65°C to +150°C
300°C
150°C
S
Unit
°C/W
°C/W
− 0.3 V to +V
JA
is
S
+ 0.3 V
Rev. C | Page 9 of 40
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (V
current (I
depends upon the particular application. The power due to
load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Airflow reduces θ
with the package leads from metal traces through holes, ground,
and power planes reduces the θ
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(121°C/W) and MSOP (θ
standard 4-layer board. θ
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
Figure 4. Maximum Power Dissipation vs. Temperature
S
). The power dissipated due to the load drive
JA
. In addition, more metal directly in contact
AMBIENT TEMPERATURE (°C)
JA
JA
values are approximations.
= 142°C/W) packages on a JEDEC
MSOP
JA
.
S
) times the quiescent
SOIC
AD8129/AD8130
D
) is the sum of the

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