OP293FS Analog Devices Inc, OP293FS Datasheet - Page 9

• Manufacturer Part Number: OP293FS
• Description: IC OPAMP GP 35KHZ DUAL 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of OP293FS

• Slew Rate: 0.015 V/µs
• Rohs Status: RoHS non-compliant
• Design Resources: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 35kHz
• Current - Input Bias: 20nA
• Voltage - Input Offset: 250µV
• Current - Supply: 30µA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 1.7 V ~ 36 V, ±0.85 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: Precision
• No. Of Amplifiers: 2
• Bandwidth: 35kHz
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +125°C
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• -3db Bandwidth: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUNCTIONAL DESCRIPTION
The OP193 family of operational amplifiers are single-supply,
micropower, precision amplifiers whose input and output ranges
both include ground. Input offset voltage (V
maximum, while the output will deliver ± 5 mA to a load. Sup-
ply current is only 17 µA.
A simplified schematic of the input stage is shown in Figure 1.
Input transistors Q1 and Q2 are PNP devices, which permit the
inputs to operate down to ground potential. The input transis-
tors have resistors in series with the base terminals to protect the
junctions from over voltage conditions. The second stage is an
NPN cascode which is buffered by an emitter follower before
driving the final PNP gain stage.
The OP193 includes connections to taps on the input load
resistors, which can be used to null the input offset voltage, V
The OP293 and OP493 have two additional transistors, Q7 and
Q8. The behavior of these transistors is discussed in the Output
Phase Reversal section of this data sheet.
The output stage, shown in Figure 2, is a noninverting NPN
“totem-pole” configuration. Current is sourced to the load by
emitter follower Q1, while Q2 provides current sink capability.
When Q2 saturates, the output is pulled to within 5 mV of
ground without an external pull-down resistor. The totem-pole
output stage will supply a minimum of 5 mA to an external
load, even when operating from a single 3.0 V power supply.
–20
–40
60
40
20
–20
60
40
20
0
100
0
10
1k
100
FREQUENCY – Hz
FREQUENCY – Hz
GAIN
±
10k
1k
PHASE
T
V
100k
V
A
S
10k
S
25°C
±15V
±15V
1M
100k
–45
–90
90
45
0
OS
) is only 75 µV
60
50
40
30
20
10
0
10
V
A
50mV
LOADS TO GND
S
V
+OS
R
L
5V T
1
CAPACITIVE LOAD – pF
V
IN
100
A
OS
–OS
R
.
150mV
25°C
L
By operating as an emitter follower, Q1 offers a high impedance
load to the final PNP collector of the input stage. Base drive to
Q2 is derived by monitoring Q1’s collector current. Transistor
Q5 tracks the collector current of Q1. When Q1 is on, Q5 keeps
Q4 off, and current source I1 keeps Q2 turned off. When Q1 is
driven to cutoff (i.e., the output must move toward V–), Q5
allows Q4 to turn on. Q4’s collector current then provides the
base drive for Q3 and Q2, and the output low voltage swing is
set by Q2’s V
+INPUT
–INPUT
1000
+OS
R
OP293,
OP493
ONLY
+OS
R
L
L
50k
10k
2k
2k
|
|
–OS
–OS
STAGE
FROM
INPUT
10000
|
|
CE,SAT
Q7
R1
R1
A
(OP193 ONLY)
B
TERMINALS
Q1
NULLING
which is about 5 mV.
I
3
Q2
I
1
–20
–40
R2
R2
OP193/OP293/OP493
60
40
20
0
Q4
Q8
A
100
B
I
2
Q3
1k
Q1
I
Q3
1
FREQUENCY – Hz
GAIN
PHASE
I
2
Q2
Q4
10k
I
3
Q5
I
D1
4
V+
OUTPUT
V–
100k
Q5
V
I
S
5
Q6
5V
I
TO
OUTPUT
STAGE
1M
6
90
45
0
–45
–90
V+
V–