AD620AR Analog Devices Inc, AD620AR Datasheet - Page 2

• Manufacturer Part Number: AD620AR
• Description: IC AMP INST LP LN 18MA 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD620AR

• Slew Rate: 1.2 V/µs
• Rohs Status: RoHS non-compliant
• Design Resources: Low Cost Programmable Gain Instrumentation Amplifier Circuit Using ADG1611 and AD620 (CN0146)
• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• -3db Bandwidth: 1MHz
• Current - Input Bias: 500pA
• Voltage - Input Offset: 30µV
• Current - Supply: 900µA
• Current - Output / Channel: 18mA
• Voltage - Supply, Single/dual (±): 4.6 V ~ 36 V, ±2.3 V ~ 18 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Bandwidth: 120kHz
• Supply Current: 1.3mA
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Programmable Gain Max: 10000
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD620
TABLE OF CONTENTS
Specifications .....................................................................................3
Absolute Maximum Ratings ............................................................5
Typical Performance Characteristics ..............................................7
Theory of Operation .......................................................................13
REVISION HISTORY
12/04—Rev. F to Rev. G
Updated Format.................................................................. Universal
Change to Features............................................................................1
Change to Product Description.......................................................1
Changes to Specifications.................................................................3
Added Metallization Photograph....................................................4
Replaced Figure 4-Figure 6 ..............................................................6
Replaced Figure 15 ............................................................................7
Replaced Figure 33 ..........................................................................10
Replaced Figure 34 and Figure 35.................................................10
Replaced Figure 37 ..........................................................................10
Changes to Table 3 ..........................................................................13
Changes to Figure 41 and Figure 42 .............................................14
Changes to Figure 43 ......................................................................15
Change to Figure 44 ........................................................................17
Changes to Input Protection section ............................................15
Deleted Figure 9...............................................................................15
Changes to RF Interference section ..............................................15
Edit to Ground Returns for Input Bias Currents section...........17
Added AD620CHIPS to Ordering Guide ....................................19
ESD Caution ..................................................................................5
Gain Selection..............................................................................16
Input and Output Offset Voltage ..............................................16
Reference Terminal .....................................................................16
Rev. G | Page 2 of 20
Outline Dimensions........................................................................19
7/03—Data Sheet changed from REV. E to REV. F
Edit to FEATURES............................................................................1
Changes to SPECIFICATIONS .......................................................2
Removed AD620CHIPS from ORDERING GUIDE ...................4
Removed METALLIZATION PHOTOGRAPH...........................4
Replaced TPCs 1–3 ...........................................................................5
Replaced TPC 12 ...............................................................................6
Replaced TPC 30 ...............................................................................9
Replaced TPCs 31 and 32...............................................................10
Replaced Figure 4 ............................................................................10
Changes to Table I...........................................................................11
Changes to Figures 6 and 7 ............................................................12
Changes to Figure 8 ........................................................................13
Edited INPUT PROTECTION section........................................13
Added new Figure 9........................................................................13
Changes to RF INTERFACE section ............................................14
Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS
section...............................................................................................15
Updated OUTLINE DIMENSIONS .............................................16
Input Protection ..........................................................................16
RF Interference............................................................................16
Common-Mode Rejection.........................................................17
Grounding....................................................................................17
Ground Returns for Input Bias Currents.................................18
Ordering Guide ...........................................................................20