AD626AR Analog Devices Inc, AD626AR Datasheet - Page 9

IC AMP DIFF LP 12MA 8SOIC

AD626AR

Manufacturer Part Number
AD626AR
Description
IC AMP DIFF LP 12MA 8SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD626AR

Slew Rate
0.22 V/µs
Mounting Type
Surface Mount
Rohs Status
RoHS non-compliant
Amplifier Type
Differential
Number Of Circuits
1
-3db Bandwidth
100kHz
Voltage - Input Offset
50µV
Current - Supply
1.5mA
Current - Output / Channel
12mA
Voltage - Supply, Single/dual (±)
2.4 V ~ 12 V, ±1.2 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
No. Of Amplifiers
1
Amplifier Case Style
SOIC
No. Of Pins
8
Programmable Gain Max
100
Supply Voltage Min
1.2V
Gain Min, V/v
10
Gain Max, V/v
100
Output Type
-
Gain Bandwidth Product
-
Current - Input Bias
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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THEORY OF OPERATION
The AD626 is a differential amplifi er con sist ing of a precision
bal anced attenuator, a very low drift preamplifi er (A1), and an
out put buffer amplifi er (A2). It has been designed so that small
differential signals can be accurately am pli fi ed and fi ltered in the
presence of large common -mode voltages (V
of any other active components.
REV. D
20V p–p
INPUT
100
90
10
0%
TPC 25. Settling Time. V
Figure 3. Settling Time Test Circuit
+IN
–IN
10k
1k
10k
200k
200k
10k
R11
R2
R1
2k
AD626
–V
41k
500
+V
5pF
C1
S
R3
S
R6
S
GND
= +5 V, G = 10
10k
4.2k
CM
R5
), without the use
C2
5pF
Figure 4. Simplifi ed Schematic
ERROR
OUT
R4
41k
R7
500
A1
+V
S
10k
R9
–9–
10k
R8
Figure 4 shows the main elements of the AD626. The signal in puts
at Pins 1 and 8 are fi rst applied to dual resistive at ten u a tors R1
through R4 whose purpose is to reduce the peak com mon-mode
voltage at the input to the preamplifi er—a feed back stage based
on the very low drift op amp A1. This allows the dif feren tial
input voltage to be accurately amplifi ed in the pres ence of large
common-mode volt ag es six times greater than that which can be
tol er at ed by the actual input to A1. As a re sult, the in put CMR
ex tends to six times the quantity (V
mode error is min i mized by precise laser-trimming of R3 and R4,
thus giving the AD626 a common-mode re jec tion ra tio (CMRR)
of at least 10,000:1 (80 dB).
To minimize the effect of spurious RF signals at the inputs due to
rectifi cation at the input to A1, small fi lter capacitors C1 and C2
are included.
The output of A1 is connected to the in put of A2 via a 100 k
(R12) resistor to facilitate the low-pass fi ltering of the sig nal of
in ter est (see Low-Pass Filtering section).
The 200 k input impedance of the AD626 requires that the source
re sis tance driving this amplifi er be low in val ue (<1 k )—this is
100k
R12
10k
R10
100
90
10
0%
TPC 26. Settling Time. V
FILTER
95k
GAIN = 100
R17
R14
555
10k
AD626
A2
R15
R13
10k
–V
S
S
– 1 V). The over all common -
S
= +5 V, G = 100
OUT
AD626

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