ADM705ARZ Analog Devices Inc, ADM705ARZ Datasheet - Page 8

• Manufacturer Part Number: ADM705ARZ
• Description: IC SUPERVISOR MPU 4.65 WD 8SOIC
• Manufacturer: Analog Devices Inc
• Type: Simple Reset/Power-On Resetr

Specifications of ADM705ARZ

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 160 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Threshold Voltage: 4.65V
• No. Of Supervisors / Monitors: 1
• Supply Voltage Range: 1V To 5.5V
• Reset Type: Active-Low
• Supply Current: 190µA
• Delay Time: 200ms
• Digital Ic Case Style: SOIC
• Current, Output: 20 mA
• Current, Supply: 190 μA
• Package Type: SOIC-8
• Power Dissipation: 470 mW
• Temperature, Operating, Range: -40 to +85 °C
• Voltage, Supply: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADM705/ADM706/ADM707/ADM708
CIRCUIT INFORMATION
POWER-FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to
the microprocessor whenever the V
threshold. An internal timer holds RESET low for 200 ms after
the voltage on V
power-on reset signal for the microprocessor. It allows time for
both the power supply and the microprocessor to stabilize after
power-up. The RESET output is guaranteed to remain valid
(low) with V
cessor is held in a stable shutdown condition as the power
supply voltage ramps up.
In addition to RESET , an active high RESET output is also
available on the ADM707/ADM708. This is the complement
of RESET and is useful for processors requiring an active high
reset signal.
MANUAL RESET
The manual reset input ( MR ) allows other reset sources, such
as a manual reset switch, to generate a processor reset. The
input is effectively debounced by the timeout period (200 ms
typical). The MR input is TTL-/CMOS-compatible, so it can
also be driven by any logic reset output.
WATCHDOG TIMER (ADM705/ADM706)
The watchdog timer circuit can be used to monitor the activity of
the microprocessor to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the watch-
dog input (WDI) line. If this line is not toggled within the timeout
period (1.60 sec), then the watchdog output ( WDO ) goes low.
The WDO can be connected to a nonmaskable interrupt (NMI)
on the processor; therefore, if the watchdog timer times out, an
interrupt is generated. The interrupt service routine should then
be used to rectify the problem.
If a RESET signal is required when a timeout occurs, the WDO
should be connected to the manual reset input ( MR ).
The watchdog timer is cleared by either a high-to-low or a low-
to-high transition on WDI. It is also cleared by RESET going
low; therefore, the watchdog timeout period begins after RESET
goes high.
RESET
WDO
V
MR
CC
CC
V
as low as 1 V. This ensures that the micropro-
Figure 13. RESET , MR , and WDO Timing
RT
CC
rises above the threshold. This functions as a
V
RT
t
RS
CC
input is below the reset
MR EXTERNALLY
DRIVEN LOW
t
RS
Rev. G | Page 8 of 12
When V
whether or not the watchdog timer has timed out. Normally, this
generates an interrupt, but it is overridden by RESET going low.
The watchdog monitor can be deactivated by floating the
watchdog input (WDI). The WDO can then be used as a low
line output, because it goes low only when V
reset threshold.
RESET
POWER-FAIL COMPARATOR
The power-fail comparator is an independent comparator that
can be used to monitor the input power supply. The comparator’s
inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input can be used to monitor the input power supply via
a resistive divider network. When the voltage on the PFI input
drops below 1.25 V, the comparator output ( PFO ) goes low,
indicating a power failure. For early warning of power failure,
the comparator can be used to monitor the preregulator input
simply by choosing an appropriate resistive divider network.
The PFO output can be used to interrupt the processor so that
a shutdown procedure is implemented before power is lost.
WDO
POWER
WDI
t
INPUT
WP
CC
falls below the reset threshold, WDO is forced low
R1
R2
POWER-FAIL
Figure 15. Power-Fail Comparator
Figure 14. Watchdog Timing
t
WD
INPUT
PFI
ADM705/ADM706/
ADM707/ADM708
RESET EXTERNALLY
TRIGGERED BY MR
1.25V
t
WD
PFO
CC
falls below the
t
RS
POWER-FAIL
OUTPUT
t
WD