ADM693AR Analog Devices Inc, ADM693AR Datasheet - Page 11

• Manufacturer Part Number: ADM693AR
• Description: IC SUPER MPU 4.4 100MA WD 16SOIC
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM693AR

• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Number Of Elements: 1
• Monitored Voltage 1 (typ): 4.5 to 5.5V
• Threshold Voltage 1 (max): 4.48V
• Watchdog Timer: Yes
• Chip Enable Signals: Yes
• Reset Active Time: 70ms
• Package Type: SOIC
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Reset Threshold Voltage (max): 4.48V
• Reset Threshold Voltage (min): 4.25V
• Family Name: ADM693
• Power Dissipation: 600mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Power Fail Detection: Yes
• Mounting: Surface Mount
• Pin Count: 16
• Supply Current: 1.95mA
• Battery Backup Switching: Yes
• Manual Reset: No
• Lead Free Status / RoHS Status: Not Compliant

REV. A
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a 3-state buffer (Figure 21a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. This would
then prevent the ADM69x from detecting that the microproces-
sor is no longer operating correctly. In most cases a better
method is to extend the watchdog period rather than disabling
the watchdog. This may be done under program control using
the circuit shown in Figure 21b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 F capacitor sets a watchdog timeout
delay of 100 seconds. When the control input is low, the OSC
SEL pin is driven high, selecting the internal oscillator. The
100 ms or the 1.6 s period is chosen, depending on which diode
in Figure 21b is used. With D1 inserted the internal timeout is
set at 100 ms, while with D2 inserted the timeout is set at 1.6 s.
BATTERY
TEST LOAD
OPTIONAL
WATCHDOG
STROBE
Figure 21a. Programming the Watchdog Input
20k
CONTROL
INPUT
Figure 20. Monitoring the Battery Status
10M
10M
V
PFI
CE
BATT
OUT
ADM69x
V
CC
+5V INPUT
POWER
WDI
CE
PFO
IN
ADM69x
LOW BATTERY
APPLIES TEST LOAD
SIGNAL TO
FROM P I/O PIN
P I/O PIN
TO BATTERY
–11–
Replacing the Backup Battery
When changing the backup battery with system power on, spuri-
ous resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the V
charge up the stray capacitance. If the voltage on V
within 50 mV of V
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following
solutions should be considered:
1. A capacitor from V
2. A resistor from V
capacitor is charging up to replace the battery. The leakage
current will charge up the external capacitor towards the V
level. The time taken is related to the charging current, the
size of external capacitor and the voltage differential between
the capacitor and the charging voltage supply.
The maximum leakage (charging) current is 1 A over tem-
perature and V
size should be chosen such that sufficient time is available to
make the battery replacement.
If a replacement time of 5 seconds is allowed and assuming a
V
on V
replacement.
Figure 22a. Preventing Spurious RESETS During
Battery Replacement
CC
Figure 21b. Programming the Watchdog Input
CONTROL
INPUT*
of 4.5 V and a V
BATTERY
BATT
from rising to within 50 mV of V
C
D1
DIFF
EXT
CC
BATT
, a reset pulse is generated.
BATT
= T
= V
BATT
C
C
t = C
to GND. This will prevent the voltage
EXT
REQD
EXT
CC
to GND. This gives time while the
D2
–V
of 3 V
EXT
= 3.33 F
V
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
(1 A/(V
BATT
BATT
ADM690–ADM695
OSC IN
OSC SEL
V
. Therefore, the capacitor
ADM69x
DIFF
CC
/I
–V
ADM69x
BATT
CC
BATT
during battery
))
BATT
pin will
reaches
CC