ADM691AR Analog Devices Inc, ADM691AR Datasheet - Page 11

• Manufacturer Part Number: ADM691AR
• Description: IC SUPER MPU 4.65 250MA 16SOIC
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM691AR

• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Number Of Elements: 1
• Monitored Voltage 1 (typ): 4.75 to 5.5V
• Threshold Voltage 1 (max): 4.73V
• Battery Backup Switching: Yes
• Watchdog Timer: Yes
• Chip Enable Signals: Yes
• Reset Active Time: 70ms
• Manual Reset: No
• Package Type: SOIC
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.5V
• Reset Threshold Voltage (max): 4.73V
• Reset Threshold Voltage (min): 4.5V
• Family Name: ADM691
• Power Dissipation: 600mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Power Fail Detection: Yes
• Mounting: Surface Mount
• Pin Count: 16
• Supply Current: 1.95mA
• Lead Free Status / Rohs Status: Not Compliant

RAM Write Protection
The CE
RAM. CE
threshold. If V
high, independent of the logic level at CE
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power in-
terruptions. The LOW LINE output goes low when V
below the reset threshold.
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
software failure occurs such that WDI not toggled a 200 ms
RESET pulse will be generated after 1.6 seconds. This typi-
cally restarts the microprocessor’s power-up routine. A new
RESET pulse is issued every 1.6 seconds until WDI is again
strobed.
The WATCHDOG OUTPUT (WDO) goes low if the watch-
dog timer is not serviced within its timeout period. Once WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI uncon-
nected. OSC IN and OSC SEL also allow other watchdog tim-
ing options.
REV. 0
OUT
OUT
line drives the Chip Select inputs of the CMOS
follows CE
CC
falls below the reset threshold, CE
IN
as long as V
CC
IN
is above the reset
. This prevents the
OUT
CC
goes
falls
–11–
RESET also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
The RESET output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector RESET bus or directly drive a
CMOS gate without an external pullup resistor.
INPUT POWER
+5V
R1
R2
BATTERY
ADM691A/ADM693A/ADM800L/M
NC
3V
Figure 24. Typical Application Circuit
0.1µF
V
GND
OSC SEL
PFI
OSC IN
LOW LINE
BATT
SYSTEM STATUS
V
CC
INDICATORS
ADM691A
ADM693A
ADM800L
ADM800M
BATT
ON
WDO
V
RESET
CE
OUT
CE
PFO
WDI
OUT
IN
RESET
0.1µF
ADDRESS
DECODE
CMOS
RAM
0.1µF
I/O LINE
NMI
RESET
A0–A15
µ P