CAT1021LI-30-G ON Semiconductor, CAT1021LI-30-G Datasheet - Page 13

• Manufacturer Part Number: CAT1021LI-30-G
• Description: IC SUPERVISR CPU 2K EEPROM 8PDIP
• Manufacturer: ON Semiconductor
• Type: Simple Reset/Power-On Resetr

Specifications of CAT1021LI-30-G

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High/Active Low
• Reset Timeout: 130 ms Minimum
• Voltage - Threshold: 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Immediate/Current Address Read
The CAT1021/22/23 address counter contains the
address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE
access was to address N, the READ immediately
following would access data from address N + 1. For
N = E = 255, the counter will wrap around to zero
and continue to clock out valid data.
CAT1021/22/23 receives its slave address infor-
mation (with the R/W ¯ ¯ bit set to one), it issues an
acknowledge,
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1021/22/23 acknowledges, the Master device
sends the START condition and the slave address
again, this time with the R/W ¯ ¯ bit set to one. The
CAT1021/22/23 then responds with its acknowledge
and sends the 8-bit byte requested. The master
device does not send an acknowledge but will
generate a STOP condition.
Figure 11. Selective Read Timing
Figure 12. Sequential Read Timing
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
BUS ACTIVITY:
SDA LINE
MASTER
BUS ACTIVITY:
then
SDA LINE
MASTER
transmits
ADDRESS
SLAVE
S
S
T
A
R
T
A
C
K
ADDRESS
the
SLAVE
DATA n
8-bit
After the
A
C
K
byte
ADDRESS (n)
A
C
K
BYTE
DATA n+1
13
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1021/22/23 sends the inital 8-
bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data. The CAT1021/22/23 will continue to output an 8-
bit byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1021/22/23 is
sent sequentially with the data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT1021/22/23
address bits so that the entire memory array can be
read during one operation.
A
C
K
R
S
T
A
T
S
C
A
K
ADDRESS
SLAVE
DATA n+2
CAT1021, CAT1022, CAT1023
A
C
K
A
C
K
DATA n
DATA n+x
N
O
C
A
K
P
S
O
P
T
Doc. No. MD-3009 Rev. P
N
O
C
A
K
S
O
P
T
P