MAX6734KALTD3+T Maxim Integrated Products, MAX6734KALTD3+T Datasheet - Page 11

• Manufacturer Part Number: MAX6734KALTD3+T
• Description: IC SUPERVISOR MPU W/WD SOT23-8
• Manufacturer: Maxim Integrated Products
• Type: Multi-Voltage Supervisorr

Specifications of MAX6734KALTD3+T

• Number Of Voltages Monitored: 3
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 3.075V, 4.625V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Monitored Voltage: 0.9 V to 5 V
• Undervoltage Threshold: 4.5 V, 3 V
• Overvoltage Threshold: 4.75 V or 3.15 V
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 210 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 0.8 V
• Supply Current (typ): 15 uA, 4 uA
• Maximum Power Dissipation: 714 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Microprocessors with bidirectional reset pins can inter-
face directly with the open-drain RST output options.
However, conditions might occur in which the push-pull
output versions experience logic contention with the
bidirectional reset pin of the µP. Connect a 10kΩ resis-
tor between RST and the µP’s reset I/O port to prevent
logic contention (Figure 5).
The MAX6730–MAX6735 µP supervisors are relatively
immune to short-duration falling V
es). Small glitches on V
MAX6730–MAX6735, preventing undesirable reset
pulses to the µP. The Typical Operating Characteristics
show Maximum Transient Duration vs. Reset Threshold
Figure 4. Watchdog Input/Output Timing Diagram (MR and WDO Connected)
RSTIN
V
V
WDO
CC
WDI
RST
CC
MR
1,
2
Interfacing to µPs with Bidirectional
Circuits with Independent Watchdog Output
(MIN)
V
Single-/Dual-/Triple-Voltage µP Supervisory
CC
Applications Information
______________________________________________________________________________________
V
TH
t
RP
Falling V
CC
_ are ignored by the
CC
< t
_ transients (glitch-
WD-L
CC
Reset Pins
Transients
< t
WD-S
> t
WD-S
Figure 5. Interfacing to µPs with Bidirectional Reset I/O
V
CC
t
MR
2
V
CC
1
V
V
t
RP
CC
CC
1
2
MAX6731
MAX6733
MAX6735
GND
RST
COMPONENTS
RESET TO
SYSTEM
OTHER
< t
WD-L
10kΩ
RESET
GND
μP
11