ADM706PAN Analog Devices Inc, ADM706PAN Datasheet - Page 6

• Manufacturer Part Number: ADM706PAN
• Description: IC SUPERVISOR MPU 2.63V WD 8DIP
• Manufacturer: Analog Devices Inc
• Type: Simple Reset/Power-On Resetr

Specifications of ADM706PAN

• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active High
• Reset Timeout: 160 ms Minimum
• Voltage - Threshold: 2.63V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T
Pin No.
1
2
3
4
5
6
7 (ADM706R/ADM706S/
ADM706T Only)
7 (ADM706P Only)
8
Mnemonic
MR
V
GND
PFI
PFO
WDI
RESET
RESET
WDO
CC
GND
V
MR
PFI
CC
1
2
3
4
(Not to Scale)
ADM706P
Figure 3. ADM706P
TOP VIEW
Description
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven
from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An
internal 70 μA pull-up current holds the input high when floating.
Power Supply Input.
Ground. Ground reference for all signals (0 V).
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less
than 1.25 V, PFO goes low. If unused, PFI should be connected to GND.
Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is
less than 1.25 V.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI
input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is
also cleared whenever reset is asserted.
Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by V
below the reset threshold or by a low signal on the MR input. RESET remains low whenever V
is below the reset threshold. It remains low for 200 ms after V
or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is
connected to MR.
Logic Output. RESET is an active high output suitable for systems that use active high reset
logic. It is the inverse of RESET.
Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of
inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes
low during low line conditions. Whenever V
soon as V
8
6
5
7
CC
WDO
RESET
WDI
PFO
goes above the reset threshold, WDO goes high immediately.
Rev. C | Page 6 of 16
Figure 4. ADM706R/ADM706S/ADM706T
GND
V
MR
PFI
CC
1
2
3
4
(Not to Scale)
ADM706R/
ADM706S/
ADM706T
TOP VIEW
CC
is below the reset threshold, WDO remains low. As
8
7
6
5
WDO
PFO
RESET
WDI
CC
goes above the reset threshold
CC
being
CC