DS1236S-10N Maxim Integrated Products, DS1236S-10N Datasheet - Page 2

• Manufacturer Part Number: DS1236S-10N
• Description: IC MICROMANAGER 10% IND 16-SOIC
• Manufacturer: Maxim Integrated Products
• Series: MicroManagerr
• Type: Battery Backup Circuitr

Specifications of DS1236S-10N

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 25 ms Minimum
• Voltage - Threshold: 4.37V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset
outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control
and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in
battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1.
PIN DESCRIPTION
PROCESSOR MODE
A distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power
consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM
and the CMOS processor. All resources would be maintained in the absence of V
is not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A
pulsed interrupt (
this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is
invoked by connecting RC to V
An NMOS processor consumes more power, and consequently may not be battery backed. In this case, it
is desirable to notify the processor of a power-fail, then keep it in reset during the loss of V
intermittent or aberrant operation. On power-up, the processor will continue to be reset until V
an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.
PIN NAME
WC/
PBRST
V
V
RST
NMI
CEO
V
RST
RC
CEI
PF
IN
PF
ST
CCO
BAT
CC
SC
NMI
+3V battery input provides nonvolatile operation of control functions.
V
+5V primary power input.
Power-fail indicator, active high, used for external power switching as shown in
Figure 9.
Power-fail indicator, active low.
Wake-up and Sleep control. Invokes low-power mode.
high for battery backed CMOS processors.
Early warning power-fail input. This voltage sense point can be tied (via resistor
divider) to a user-selected voltage.
Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending
power failure.
Strobe input. A high-to-low transition will reset the watchdog timer, indicating that
software is still in control.
Chip enable output. Used with nonvolatile SRAM applications.
Chip enable input.
Pushbutton reset input.
Active low reset output.
Reset control input. Determines reset output. Normally low for NMOS processors and
Active high reset output.
CC
) is issued to allow the CMOS processor to invoke a sleep mode to save power. For
output for nonvolatile SRAM applications.
CCO
.
2 of 19
DESCRIPTION
CC
. A power-down reset
CC
. This avoids
CC
reaches
DS1236