CAT1163WI-28-GT3 ON Semiconductor, CAT1163WI-28-GT3 Datasheet
CAT1163WI-28-GT3
Specifications of CAT1163WI-28-GT3
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CAT1163WI-28-GT3 Summary of contents
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Supervisory Circuits with I Precision Reset Controller and Watchdog Timer (16K) FEATURES Watchdog timer input (WDI) 2 400kHz I C bus compatible 2.7V to 6.0V operation Low power CMOS technology 16-Byte page write buffer Built-in inadvertent write protection — V ...
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CAT1163 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground V with Respect to Ground CC Package Power Dissipation Capability (T Lead Soldering Temperature (10 seconds) (3) Output Short Circuit ...
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D.C. OPERATING CHARACTERISTICS V = 2.7V to 6.0V, unless otherwise specified. CC Symbol Parameter I Power Supply Current CC I Standby Current SB I Input Leakage Current LI I Output Leakage Current LO V Input Low Voltage IL V Input ...
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CAT1163 WRITE CYCLE LIMITS Symbol Parameter t Write Cycle Time WR The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the ...
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PIN DESCRIPTION WDI: WATCHDOG INPUT If there is no transition on the WDI for more than 1.6 seconds, the watchdog timer times out. WP: WRITE PROTECT If the pin is tied to V the entire memory array CC becomes Write ...
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CAT1163 Hardware Data Protection The CAT1163 is designed with the following hardware data protection features to provide a high degree of data integrity. (1) The CAT1163 features a WP pin. When the WP pin is tied high the entire memory ...
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FUNCTIONAL DESCRIPTION 2 The CAT1163 supports the I C Bus data transmis– sion protocol. This Inter-Integrated Circuit Bus proto– col defines any device that sends data to the bus transmitter and any device receiving data to be ...
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CAT1163 Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT1163 ...
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Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1163 initiates the internal write cycle. ...
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CAT1163 Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses ...
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PACKAGE OUTLINE DRAWINGS (1)(2) PDIP 8-Lead 300mils (L) PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. © 2009 SCILLC. All rights reserved. Characteristics subject ...
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CAT1163 (1)(2) SOIC 8-Lead 150mils (W) PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. Doc. No. MD-3003 Rev. I SYMBOL A A1 ...
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... Reset Threshold Voltage CAT1163LI-25-G CAT1163LI-28-G CAT1163LI-30-G CAT1163LI-42-G CAT1163LI-45-G CAT1163WI-25-GT3 CAT1163WI-28-GT3 CAT1163WI-30-GT3 CAT1163WI-42-GT3 CAT1163WI-45-GT3 Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT1163WI-30-GT3 (SOIC, Industrial Temperature 3.15V, NiPdAu, Tape & Reel, 3,000/Reel) ...
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... Update Package Outline Update Package Outline Drawings 11/28/07 F Update Example of Ordering Information Add “MD-“ to document number 10-Nov-08 G Change logo and fine print to ON Semiconductor 04-May-09 H Update Watchdog Timer 31-Jul-09 I Update Ordering Information ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...