ADP3303ARZ-5 Analog Devices Inc, ADP3303ARZ-5 Datasheet - Page 6

• Manufacturer Part Number: ADP3303ARZ-5
• Description: IC REG LDO 200MA 5V 8-SOIC
• Manufacturer: Analog Devices Inc
• Series: anyCAP®r

Specifications of ADP3303ARZ-5

• Design Resources: Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102) Precision Weigh Scale Design Using AD7191 with Internal PGA (CN0118) Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) Precision Weigh Scale Design Using AD7195 with Internal PGA and AC Excitation (CN0155)
• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: Up to 12V
• Voltage - Dropout (typical): 0.18V @ 200mA
• Number Of Regulators: 1
• Current - Output: 200mA
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Primary Input Voltage: 12V
• Output Voltage Fixed: 5V
• Dropout Voltage Vdo: 150mV
• No. Of Pins: 8
• Output Current: 200mA
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADP3303
THEORY OF OPERATION
The new anyCAP LDO ADP3303 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2, which is
varied to provide the available output voltage options. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibil-
ity on the tradeoff of noise sources that leads to a low noise
design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1, and a second divider consist-
ing of R3 and R4, the values are chosen to produce a tempera-
ture stable output. This unique arrangement specifically corrects
for the loading of the divider so that the error resulting from
base current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR val-
ues for the output capacitor because they are difficult to sta-
bilize due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value, required to keep conventional LDOs
stable, changes depending on load and temperature. These ESR
limitations make designing with LDOs more difficult because
of their unclear specifications and extreme variations over
temperature.
IN
ADP3303
NONINVERTING
WIDEBAND
DRIVER
Q1
Figure 20. Functional Block Diagram
COMPENSATION
CAPACITOR
g
m
PTAT
V
OS
R4
(V
ATTENUATION
BANDGAP
GND
CURRENT
R3
PTAT
/V
D1
OUT
R1
R2
)
OUT
(a)
C
R
LOAD
LOAD
–6–
This is no longer true with the ADP3303 anyCAP LDO. It can
be used with virtually any capacitor, with no constraint on the
minimum ESR. The innovative design allows the circuit to be
stable with just a small 0.47 F capacitor on the output. Addi-
tional advantages of the pole splitting scheme include superior line
noise rejection and very high regulator gain, which leads to excel-
lent line and load regulation. An impressive 1.4% accuracy is
guaranteed over line, load and temperature.
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to standard solutions
that give warning after the output has lost regulation, the
ADP3303 provides improved system performance by enabling the
ERR Pin to give warning before the device loses regulation.
As the chip’s temperature rises above 165 C, the circuit acti-
vates a soft thermal shutdown, indicated by a signal low on the
ERR Pin, to reduce the current to a safe level.
To reduce the noise gain of the loop, the node of the main di-
vider network (a) is made available at the noise reduction (NR)
pin, which can be bypassed with a small capacitor (10 nF–100 nF).
APPLICATION INFORMATION
Capacitor Selection
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3303 is stable with a wide range of capacitor values, types
and ESR. A capacitor as low as 0.47 F is all that is needed for
stability; larger capacitors can be used if high output current
surges are anticipated. The ADP3303 is stable with extremely
low ESR capacitors (ESR
Capacitors (MLCC) or OSCON.
Input Bypass Capacitor: an input bypass capacitor is not
required; for applications where the input source is high imped-
ance or far from the input pins, a bypass capacitor is recom-
mended. Connecting a 0.47 F capacitor from the input pins to
ground reduces the circuit’s sensitivity to PC board layout. If a
larger value output capacitor is used, then a larger value input
capacitor is also recommended.
Noise Reduction
A noise reduction capacitor (C
the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in
the 10 nF–100 nF range provide the best performance. Since
the noise reduction pin (NR) is internally connected to a high
impedance node, any connection to this node should be carefully
done to avoid noise pickup from external sources. The pad
connected to this pin should be as small as possible. Long PC
board traces are not recommended.
V
IN
1 F
C1
+
Figure 21. Noise Reduction Circuit
7
8
ADP3303-5.0
IN
SD
SD
5
OFF
ON
ERR
OUT
GND
0), such as Multilayer Ceramic
NR
4
NR
3
1
2
6
) can be used to further reduce
R1
330k
C
10nF
NR
E
OUT
+
C2
10 F
V
OUT
= 5V
REV. A