LX8384-00CDD Microsemi Analog Mixed Signal Group, LX8384-00CDD Datasheet - Page 6

• Manufacturer Part Number: LX8384-00CDD
• Description: IC REG LDO ADJ 5A TO263
• Manufacturer: Microsemi Analog Mixed Signal Group

Specifications of LX8384-00CDD

• Applications: Converter, Intel Pentium® P54C-VRE
• Voltage - Input: 4.75 ~ 10 V
• Number Of Outputs: 1
• Voltage - Output: Adjustable
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TO-263-3, D²Pak (3 leads + Tab), TO-263AA
• Current - Output: 5A (Min)
• Regulator Topology: Positive Adjustable
• Voltage - Dropout (typical): 1.2V @ 5A
• Number Of Regulators: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Other names: LX8384-00CDDR; LX8384-00CDDR

Copyright © 2000
Rev. 2.1f, 2006-01-20
OVERLOAD RECOVERY (continued)
RIPPLE REJECTION
OUTPUT VOLTAGE
voltage across the regulator at the time the short circuit is
removed from the output. If this limited current is not sufficient
to develop the designed voltage across the output resistor, the
voltage will stabilize at some lower value, and will never reach
the designed value. Under these circumstances, it may be
necessary to cycle the input voltage down to zero in order to
make the regulator output voltage return to regulation.
between the ADJ pin and ground. The value of the capacitor
should be chosen so that the impedance of the capacitor is equal
in magnitude to the resistance of R1 at the ripple frequency. The
capacitor value can be determined by using this equation:
this case, 15µF. When an ADJ pin bypass capacitor is used,
output ripple amplitude will be essentially independent of the
output voltage. If an ADJ pin bypass capacitor is not used, output
ripple will be proportional to the ratio of the output voltage to the
reference voltage:
pin were to be bypassed to ground with a properly selected
capacitor.
between the output and the adjust terminal (See Figure 2). By
placing a resistor, R1, between these two terminals, a constant
current is caused to flow through R1 and down through R2 to set
the overall output voltage. Normally this current is the specified
minimum load current of 10mA. Because I
constant when compared with the current through R1, it
represents a small error and can usually be ignored.
where:
At a Ripple frequency of 120Hz, with R1= 100Ω:
where:
For example, if V
Ripple rejection can be improved by connecting a capacitor
The closest equal or larger standard value should be used, in
Output ripple will be twice as bad as it would be if the ADJ
The LX8384/84A/84B ICs develop a 1.25V reference voltage
TM
C
F
R1 ≡ the value of resistor R1 in ohms
M
V
C
R
REF
=
≡ the value of the capacitor in Farads; select
≡ the ripple frequency in Hz
≡ a multiplier for the ripple seen when the
= 1.25V
(
. 6
OUT
28
an equal or larger standard value.
ADJ pin is optimally bypassed.
C
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: [phone]
= 2.5V the output ripple will be:
×
M
=
120
(
M
. 6
=
1
Hz
28
. 1
=
2
25
5 .
×
V
×
V
1
V
OUT
F
100
REF
V
R
×
=
A P P L I C A T I O N N O T E S
Ω
R
2
1
)
)
=
ADJ
13
3 .
is very small and
μF
Integrated Products Division
Microsemi Inc.
®
LOAD REGULATION
devices, it is not possible to provide true remote load sensing.
Load regulation will be limited by the resistance of the wire
connecting the regulator to the load. The data sheet specification
for load regulation is measured at the bottom of the package.
Negative side sensing is a true Kelvin connection, with the
bottom of the output divider returned to the negative side of the
load. Although it may not be immediately obvious, best load
regulation is obtained when the top of the resistor divider, (R1), is
connected directly to the case of the regulator, not to the load.
This is illustrated in Figure 3. If R1 were connected to the load,
the effective resistance between the regulator and the load would
be:
parasitic resistance appears as its actual value, rather than the
higher R
5A Low Dropout Positive Regulators
where:
FIGURE 3 - CONNECTIONS FOR BEST LOAD REGULATION
Because the LX8384/84A/84B regulators are three-terminal
When the circuit is connected as shown in Figure 3, the
( C O N T I N U E D )
V
V
IN
IN
Peff
FIGURE 2 - BASIC ADJUSTABLE REGULATOR
V
.
IN
OUT
P
R
RODUCTION
P
IN
=
V
LX8384x
R
REF
ADJ
≡
Peff
⎛
⎜ ⎜
⎝
LX8384x
1
50µA
=
I
Actual parasitic line resistance.
ADJ
ADJ
+
R
R
R
P
D
1
2
×
ATA
⎞
⎟
⎠
⎛
⎜
⎝
+
R
I
R2
R1
2
ADJ
S
R
OUT
+
HEET
1
R
R
2
1
Connect R1 to
Case of Regulator
Connect R2 to
Load
V
OUT
REF
⎞
⎟
⎠
R
P
Resistance
Parasitic Line
LX8384x-xx
R1
R2
V
OUT
R
L
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