S-1112B49MC-L7ITFG Seiko Instruments, S-1112B49MC-L7ITFG Datasheet - Page 15

• Manufacturer Part Number: S-1112B49MC-L7ITFG
• Description: IC REG LDO 150MA 4.9V SOT23-5
• Manufacturer: Seiko Instruments

Specifications of S-1112B49MC-L7ITFG

• Regulator Topology: Positive Fixed
• Voltage - Output: 4.9V
• Voltage - Input: Up to 6.5V
• Voltage - Dropout (typical): 0.19V @ 100mA
• Number Of Regulators: 1
• Current - Output: 150mA (Min)
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -

The S-1112/1122 Series requires an output capacitor between the VOUT and VSS pins for phase
compensation. A ceramic capacitor with a capacitance of 0.47 μF or more can be used. Even if using an OS
capacitor, tantalum capacitor, or aluminum electrolytic capacitor, a capacitance of 0.47 μF or more and an ESR
of 10 Ω or less are required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor.
When selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature
characteristics, on the actual device.
Rev.6.0
Selection of Output Capacitor (C
3. Shutdown pin (ON/OFF pin)
This pin starts and stops the regulator.
When the ON/OFF pin is set to the shutdown level, the operation of all internal circuits stops, and the built-
in P-channel MOS FET output transistor between the VIN pin and VOUT pin is turned off to substantially
reduce the current consumption. The VOUT pin becomes the V
resistance of several MΩ between the VOUT pin and VSS pin.
The structure of the ON/OFF pin is as shown in Figure 13. Since the ON/OFF pin is neither pulled down
nor pulled up internally, do not use it in the floating state. In addition, note that the current consumption
increases if a voltage of 0.3 V to V
used, connect it to the VSS pin if the logic type is “A” and to the VIN pin if it is “B”.
Logic Type
ON/OFF
HIGH RIPPLE-REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
_00
A
A
B
B
Figure 13
“H”: Power off
“H”: Power on
“L”: Power on
“L”: Power off
ON/OFF Pin
VSS
VIN
IN
Internal Circuits
– 0.3 V is applied to the ON/OFF pin. When the ON/OFF pin is not
Operating
Operating
Stopped
Stopped
Seiko Instruments Inc.
L
)
Table 8
VOUT Pin Voltage
Set value
Set value
V
V
SS
SS
level
level
SS
level due to the internally divided
Current Consumption
S-1112/1122 Series
I
I
I
I
SS1
SS2
SS2
SS1
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