CS8126-1YDPSR7G ON Semiconductor, CS8126-1YDPSR7G Datasheet - Page 7

• Manufacturer Part Number: CS8126-1YDPSR7G
• Description: IC REG LDO LIN 750MA 5V D2PAK-7
• Manufacturer: ON Semiconductor

Specifications of CS8126-1YDPSR7G

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: 6 ~ 26 V
• Voltage - Dropout (typical): 0.35V @ 500mA
• Number Of Regulators: 1
• Current - Output: 500mA
• Current - Limit (min): 750mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: TO-263-7, D²Pak (7 leads + Tab), TO-263CA
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 60 V
• Output Voltage: 5 V
• Output Type: Fixed
• Dropout Voltage (max): 0.6 V at 500 mA
• Output Current: 750 mA
• Line Regulation: 50 mV
• Load Regulation: 50 mV
• Voltage Regulation Accuracy: 3 %
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CS8126-1YDPSR7GOS; CS8126-1YDPSR7GOS; CS8126-1YDPSR7GOSTR

Reset and Delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1.0 V.
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
voltage falls below V
transistor to be in the ON (saturation) state. When the output
voltage rises above V
output transistor to go into the OFF state if allowed by the
RESET Delay circuit.
RESET Delay Circuit
capacitor) delay on the RESET output lead. The Delay lead
provides source current to the external delay capacitor only
when the “Low Voltage Inhibit” circuit indicates that output
Stability Considerations
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR, can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
The CS8126 RESET function, has hysteresis on both the
The RESET circuit output is an open collector type with
This circuit monitors output voltage, and when the output
This circuit provides a programmable (by external
The output or compensation capacitor helps determine
The capacitor value and type should be based on cost,
** C
* C
1
2
is required if the regulator is far from the power source filter.
is required for stability.
RT(ON)
RT(OFF)
, this circuit permits the RESET
C
100 nF
1
, causes the RESET output
*
Delay
0.1 mF
Figure 13. Application Diagram
CIRCUIT DESCRIPTION
APPLICATION NOTES
V
Delay
IN
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CS8126
7
GND
voltage is above V
current to ground (used to discharge the delay capacitor).
The discharge current is latched ON when the output voltage
falls below V
discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled RESET pulse is generated following
detection of an error condition. The circuit allows the
RESET output transistor to go to the OFF (open) state only
when the voltage on the Delay lead is higher than V
the formula:
16 ms to 48 ms. The tolerance of the capacitor must be taken
into account to calculate the total variation in the delay time.
temperatures (−25°C to −40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
applications circuit should work for most applications,
however it is not necessarily the optimized solution.
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
The Delay time for the RESET function is calculated from
If C
The value for the output capacitor C
To determine an acceptable value for C
Delay
RESET
V
OUT
= 0.1 mF, Delay time (ms) = 32 ms ± 50%: i.e.
Delay time +
Delay time + C Delay
RT(OFF)
RT(ON)
R
4.7 kW
. The Delay capacitor is fully
C Delay
RST
. Otherwise, the Delay lead sinks
I Charge
V Delay Threshold
3.2
2
shown in the test and
C
10 mF to 100 mF
10 5
2
**
2
for a particular
DC(H1)
.