AT91SAM7S64C-MU-999 Atmel, AT91SAM7S64C-MU-999 Datasheet - Page 31

• Manufacturer Part Number: AT91SAM7S64C-MU-999
• Description: IC ARM7 MCU FLASH 64K 64QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S64C-MU-999

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFN
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: AT91SAM7S64B-MU-999; AT91SAM7S64B-MU-999

9.4
6175IS–ATARM–30-Aug-10
Advanced Interrupt Controller
Figure 9-4.
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Individually maskable and vectored interrupt sources
• 8-level Priority Controller
• Vectoring
• Protect Mode
• Fast Forcing
• General Interrupt Mask
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.)
– Other sources control the peripheral interrupts or external interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive external
– Drives the normal interrupt of the processor
– Handles priority of the interrupt sources
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes interrupt service routine branch and execution
– One 32-bit vector register per interrupt source
– Interrupt vector register reads the corresponding current interrupt vector
– Easy debugging by preventing automatic operations
– Permits redirecting any interrupt source on the fast interrupt
– Provides processor synchronization on events without triggering an interrupt
sources
Power Management Controller Block Diagram
MAINCK
MAINCK
PLLCK
PLLCK
SLCK
SLCK
PLLCK
Master Clock Controller
Programmable Clock Controller
/1,/2,/4,...,/64
Prescaler
USB Clock Controller
AT91SAM7S Series Summary
/1,/2,/4,...,/64
ON/OFF
Divider
/1,/2,/4
Prescaler
Processor
Idle Mode
Controller
Clock Controller
Clock
Peripherals
ON/OFF
PCK
int
MCK
periph_clk[2..14]
pck[0..2]
usb_suspend
UDPCK
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