71M6521FE-IGT/F Maxim Integrated Products, 71M6521FE-IGT/F Datasheet - Page 44

• Manufacturer Part Number: 71M6521FE-IGT/F
• Description: IC ENERGY METER 32K FLASH 64LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FE-IGT/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three-Wire EEPROM Interface
A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with
DIO_EEX=3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 58. When
EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending
on the values of the EECTRL bits.
The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All commands
begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS.
Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and
EEDATA. When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will
be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should then immediately
issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state.
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Control
3-0
Bit
7
6
5
4
SDATA output Z
SDATA (output)
SDATA output Z
SDATA (output)
EECTRL Byte Written
SCLK (output)
EECTRL Byte Written
SCLK (output)
Write -- With HiZ
Write -- No HiZ
CNT[3:0]
BUSY (bit)
Name
BUSY (bit)
BUSY
WFR
HiZ
RD
Read/Write
Figure 10: 3-Wire Interface. Write Command, HiZ=1
Figure 9: 3-Wire Interface. Write Command, HiZ=0.
W
W
W
W
R
Table 58: EECTRL bits for 3-wire interface
D7
D7
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
Asserted while serial data bus is busy. When the BUSY bit falls, an INT5
interrupt occurs.
Indicates that the SD signal is to made high impedance immediately after
the last SCK rising edge.
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent
MSB first to EEPROM, shifted out of EEDATA’s MSB. If CNT is zero,
SDATA will simply obey the HiZ bit.
D6
D6
CNT Cycles (6 shown)
CNT Cycles (6 shown)
(LoZ)
D5
(LoZ)
D5
D4
D4
D3
D3
D2
D2
71M6521DE/DH/FE Data Sheet
INT5
INT5
(HiZ)
Rev 2