73S8009R-DB Maxim Integrated Products, 73S8009R-DB Datasheet - Page 12

• Manufacturer Part Number: 73S8009R-DB
• Description: BOARD DEMO 73S8009R 28-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of 73S8009R-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

73S8009R Demo Board User Manual
5 73S8009R Demo Board Schematics, PCB Layouts and Bill of Materials
5.1
12
J1 and J3 are placed on the bottom.
are placed on the top side.
J1 and J3 must be aligned with J8 and J9 on the
1121 evaluation board (E1121T8) respectivly in
order for this board to be stacked on it.
J1 must be aligned with J2 and J3 must be
aligned with J4 in order for this daughter
board to be stacked on another.
CMDVCC5
CMDVCC3
RESET
PWRDN
+3.3V
RSTIN
SCLK
SSM_110_L_SV
TSM_110_01_L_SV
SSM_110_L_SV
TSM_110_01_L_SV
TEST
RDY
GND
SIO
SC4
SC8
OFF
GND
GND
GND
+5V
+5V
CS
Schematics
J1
10
J2
10
J3
10
J4
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCLK
SIO
S_C4
S_C8
INT2
5V
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
GND
5.0V
3.3V
C3
C10
J2 and J4
10uF
10uF
CARD DETECT
POLARITY SELECT
Figure 4: 73S8009R Electrical Schematic
TP2
1
2
20K
R1
JP5
JP6
PWRDN
PULL-DOWN
SELECT
1
2
3
1
2
3
GND
VDD
PRES
PRES
U1
10
11
12
13
14
1
2
3
4
5
6
7
8
9
R10
Ru
R13
Rd
73S8009R
J7
BNC
CS
RESET
N/C
0FF
I/OUC
AUX1UC
AUX2UC
CMDVCC5
CMDVCC3
RSTIN
CLKIN
RDY
PWRDN
TEST
VDD
1
R2
49.9
CLKIN
SELECT
27pF
C12
1
2
3
JP1
PRES
PRES
SCLK
EXTCLK
AUX1
AUX2
GND
GND
VDD
VCC
VPC
RST
CLK
N/C
N/C
I/O
I/O
C8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C1, C2 and C8 must be placed
within 5mm of the U1 pins and
connected by thick track (wider
than 0.5mm)
27pF
C13
TP4
TP6
1
2
1
2
J5
Smart Card Connector
VPC
SELECT
TP1
3.3uF
C11
5V
R7
TP3
TP5
TP7
TP8
C1
C2
J6
UM_8009R_065
0
1
2
1
2
1
2
1
2
5.0V
SIM/SAM Connector
10uF
VCC
RST
CLK
C4
0.1uF
PGND
C8
0.1uF
TP3 to TP8 to be placed
very close to the pads
of J5
Rev. 1.2
R4
R8
Ru
R11
Rd
0
VDD
R9
Ru
R12
Rd
VDD
SELECT
TP9
These resistors are
not populated
3.3V
3.3V