MGA-85563-BLKG Avago Technologies US Inc., MGA-85563-BLKG Datasheet - Page 8

• Manufacturer Part Number: MGA-85563-BLKG
• Description: AMP RFIC LNA GAAS 3V SOT-363
• Manufacturer: Avago Technologies US Inc.
• Type: General Purpose Amplifierr

Specifications of MGA-85563-BLKG

• P1db: 0.9dBm
• Noise Figure: 1.6dB
• Package / Case: SC-70-6, SC-88, SOT-363
• Current - Supply: 15mA ~ 20mA
• Frequency: 0Hz ~ 6GHz
• Gain: 18dB
• Rf Type: Cellular, PCS, WLAN
• Test Frequency: 2GHz
• Voltage - Supply: 2.7V ~ 3.6V
• Mounting Style: SMD/SMT
• Technology: Low Noise Amplifier
• Number Of Channels: 1
• Operating Frequency: 6000 MHz
• Operating Supply Voltage: 3 V
• Supply Current: 20 mA @ 3 V
• Manufacturer's Type: Low Noise Amplifier
• Frequency (max): 6GHz
• Operating Supply Voltage (typ): 3V
• Package Type: SOT-363
• Mounting: Surface Mount
• Pin Count: 6
• Noise Figure (typ): 1.6(Min)@6000MHzdB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1957; MGA-85563-BLKG

The current is increased only in the second stage of the
MGA-85563. Bias current for the first stage remains fixed
and thus the input impedance and noise figure for the
amplifier are unaffected by the increase in bias current.
The output match is also generally unaffected by in-
creased device current and remains quite good over the
complete operating current and frequency range.
PCB Layout
A recommended PCB pad layout for the miniature
SOT-363 (SC-70) package that is used by the MGA-85563
is shown in Figure 17.
0.035
Figure 17. Recommended PCB Pad Layout for Avago’s SC70 6L/SOT-363
Products.
This layout provides ample allowance for package
placement by automated assembly equipment without
adding parasitics that could impair the high frequency
RF performance of the MGA-85563. The layout is shown
with a footprint of a SOT-363 package superimposed on
the PCB pads for reference.
Starting with the package pad layout in Figure 17, an
RF layout similar to the one shown in Figure 18 a good
starting point for microstripline designs using the MGA-
85563 amplifier.
Input
Figure 18. RF Layout.
8
RF
R
b
0.026
0.016
85
0.075
Output
RF
Adequate grounding of Pins 1, 2, and 5 of the RFIC are
important to maintain device stability and RF perfor-
mance. Each of the ground pins should be connected to
the groundplane on the backside of the PCB by means
of plated through holes (vias). The ground vias should
be placed as close to the package terminals as practical.
At least one via should be located next to each ground
pin to assure good RF grounding. It is a good practice
to use multiple vias to further minimize ground path in-
ductance.
If the adjustable current feature is to be used, an addi-
tional ground pad located near the Rbias pin may be
used to connect the current-setting resistor (Rb) directly
from the Rbias pin to ground. (The ground pad for Pin
5 could also be used for this purpose.) Note that when
using an external resistor, the Rbias pad should not be
bypassed to ground. Doing so could result in undesir-
able resonances in the amplifier gain response.
If for any reason the R
ately adjacent to the MGA-85563 (such as in the case of
remote current adjustment or to implement dynamic
control of the device’s linearity), then a small series re-
sistor (e.g., 10 Ω) should be located near the R
de-Q the connection from the MGA-85563 to the exter-
nal current-setting circuit.
If the adjustable current feature of the MGA-85563 is not
used, the R
the PCB pad for the R
to provide a mechanical attachment, such as shown in
Figure 17. If a large pad or length of line is connected to
the R
interact with the internal circuitry of the MGA-85563 to
create an undesirable resonance in the gain response of
the amplifier.
While it might be considered an effective RF practice,
it is recommended that the PCB pads for the ground
pins not be connected together underneath the body
of the package. In many cases, it is important that the
individual stages within the device be grounded sepa-
rately to prevent inadvertent interstage feedback. In ad-
dition, PCB traces hidden under the package cannot be
adequately inspected for SMT solder bridging or quality.
bias
pad, a potential exists for the pad parasitics to
bias
pin should be left open. When not used,
bias
b
pin should only be large enough
resistor is not located immedi-
bias
pin to