ATA555814C-DDB Atmel, ATA555814C-DDB Datasheet - Page 6

• Manufacturer Part Number: ATA555814C-DDB
• Description: IC IDIC 1KBIT R/W DIE
• Manufacturer: Atmel

Specifications of ATA555814C-DDB

• Function: Read/Write
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.7
2.7.1
6
Security Levels
ATA5558
Password Protection
The blocks 59, 60 and 61 contain Atmel’s manufacturer’s serial number (MSN). The top 4 digits
of block 61 specifiy the IC code of this product. The following byte of block 61 is fixed to E0h
which is the allocation class (ACL) for registered IC manufacturers as defined in TDR 15963-1;
followed by the manufacturer code (MFC), which compliant with ISO/IEC 7816-6/AM1, is defined
as 15h for Atmel. The remaining two blocks contain a 64-bit Atmel unique traceability code. The
data is divided in several sub-groups, a 36-bit lot ID code, a 5-bit wafer number and a 18-bit
sequential die number which represents the physical location of the chip on the processed wafer.
The ICR nibble (4 bits) of this manufacturer serial number (MSN) is used for the IC refer-
ence/version (ICR).
The unique tag identifier (Tag ID) blocks provide an address code with which each tag can be
individually identified and interrogated. These codes are programmed by either the tag system
administrator or the tag manufacturer into blocks 56 to 58. The allocation of individual Identifica-
tion codes must be handled so that an interrogator can never be confronted with two tags with
identical Tag IDs. This is an important issue as the Tag ID is used as the basis for accessing and
sorting tags during anticollision commands GetID, Select and SelectGroup.
The Atmel traceability code (blocks 60 and 59) itself provides a means of unique chip identifica-
tion so that this data content can be used as the Tag ID or a part of the Tag ID by copying it or
part of it into blocks 56 and 57.
The Tag ID code is located in blocks 56 to 58. It is MSB aligned so that it may occupy between
16 and 96 bits (see
(see
detection loop so it should be adjusted to suit system requirements. The default preprogrammed
Tag ID length is 64 bits. The anticollision algorithm is based on a bit by bit binary tree elimination,
carried out in parallel on all the Tag IDs within the interrogator field. This starts with the MSB of
the Tag ID (always in bit position 31 of block 56) and continues through to bit position 0 of block
58 or until the Tag ID LSB, indicated by the configuration Tag ID length, is reached.
The ATA5558 has three levels of security. Firstly, the restricted password access which pre-
vents unauthorized access to both user and system data but allows authorized access using the
correct password. Then a block orientated absolute write lock protection (lock bits) and finally
the Master Key with a security code which has to be set in the configuration block accordingly
(see
The user memory is subdivided into continuous page areas which can be configured so that
write or read/write operations on blocks within these pages can only be carried out after the
appropriate password has been transmitted to the tag (LoginRead or LoginWrite command). The
read and write password protections are independent and user definable. The read and write
passwords are found in blocks 54 and 55 and the page security levels are defined in the Page
Security register of block 62 (see
Figure 2-7 on page
Table 2-2 on page 8
Figure 2-4 on page
9) and has an impact on the time required to complete the anticollision
and
Figure 2-7 on page
Figure 2-6 on page
5). This Tag ID length is set in the configuration block
9).
7).
4681E–RFID–11/09