ATA5745-EK

Manufacturer Part NumberATA5745-EK
DescriptionBOARD RCVR 433MHZ RKE/TPMS
ManufacturerAtmel
TypeReceiver, ASK/FSK
ATA5745-EK datasheets
 

Specifications of ATA5745-EK

Frequency433MHz ~ 435MHzFor Use With/related ProductsATA5745
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Features
Transparent RF Receiver ICs for 315 MHz (ATA5746) and 433.92 MHz (ATA5745) With
High Receiving Sensitivity
Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter
High FSK/ASK Sensitivity:–105 dBm (ATA5746, FSK, 9.6 Kbits/s, Manchester, BER 10
–114 dBm (ATA5746, ASK, 2.4 Kbits/s, Manchester, BER 10
–104 dBm (ATA5745, FSK, 9.6 Kbits/s, Manchester, BER 10
–113 dBm (ATA5745, ASK, 2.4 Kbits/s, Manchester, BER 10
Supply Current: 6.5 mA in Active Mode (3V, 25°C, ASK Mode)
Data Rate: 1 Kbit/s to 10 Kbits/s Manchester ASK, 1 Kbit/s to 20 Kbits/s Manchester
FSK With Four Programmable Bit Rate Ranges
Switching Between Modulation Types ASK/FSK and Different Data Rates Possible in
1 ms Typically, Without Hardware Modification on Board to Allow Different Modulation
Schemes for RKE, TPMS
Low Standby Current: 50 µA at 3V, 25°C
ASK/FSK Receiver Uses a Low-IF Architecture With High Selectivity, Blocking, and
Low Intermodulation (Typical 3-dB Blocking 68.0 dBC at ±3 MHz/74.0 dBC at
±20.0 MHz, System I1dBCP = –31 dBm/System IIP3 = –24 dBm)
Telegram Pause Up to 52 ms Supported in ASK Mode
Wide Bandwidth AGC to Handle Large Out-of-band Blockers above the System I1dBCP
440-kHz IF Frequency With 30-dB Image Rejection and 420-kHz IF Bandwidth to
Support PLL Transmitters With Standard Crystals or SAW-based Transmitters
RSSI (Received Signal Strength Indicator) With Output Signal Dynamic Range of 65 dB
Low In-band Sensitivity Change of Typically ±2.0 dB Within ±160-kHz Center
Frequency Change in the Complete Temperature and Supply Voltage Range
Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer
Fast and Stable XTO Start-up Circuit (> –1.4 k Worst-case Start Impedance)
Clock Generation for Microcontroller
ESD Protection at all Pins (±4 kV HBM, ±200V MM, ±500V FCDM)
Dual Supply Voltage Range: 2.7V to 3.3V or 4.5V to 5.5V
Temperature Range: –40°C to +105°C
Small 5 mm
5 mm QFN24 Package
Applications
Automotive Keyless Entry and Tire Pressure Monitoring Systems
Alarm, Telemetering and Energy Metering Systems
Benefits
Supports Header and Blanking Periods of Protocols Common in RKE and TPM
Systems (Up to 52 ms in ASK Mode)
All RF Relevant Functions are Integrated. The Single-ended RF Input is Suited for Easy
Adaptation to
/ 4 or Printed-loop Antennas
Allows a Low-cost Application With Only 8 Passive Components
Suitable for use in a Receiver for Joint RKE and TPMS
Optimal Bandwidth Maximizes Sensitivity while Maintaining SAW Transmitter
Compatibility
Clock Output Provides an External Microcontroller Crystal-precision Time Reference
Well Suited for Use With PLL Transmitter ATA5756/ATA5757
-3
)
-3
)
-3
)
-3
)
UHF ASK/FSK
Receiver
ATA5745
ATA5746
Preliminary
4596B–RKE–06/07

ATA5745-EK Summary of contents

  • Page 1

    ... Features • Transparent RF Receiver ICs for 315 MHz (ATA5746) and 433.92 MHz (ATA5745) With High Receiving Sensitivity • Fully Integrated PLL With Low Phase Noise VCO, PLL, and Loop Filter • High FSK/ASK Sensitivity:–105 dBm (ATA5746, FSK, 9.6 Kbits/s, Manchester, BER 10 – ...

  • Page 2

    ... Because of the highly integrated design, the only required RF components are for the purpose of receiver antenna matching. ATA5745 and ATA5746 support Manchester bit rates of 1 Kbit Kbits/s in ASK and 1 Kbit Kbits/s in FSK mode. The four discrete bit rate passbands are selectable and cover 1 ...

  • Page 3

    ... GND 13 LNA_GND 14 LNA_IN 15 SENSE 16 SENSE_CTRL 17 RSSI 18 TEST3 BR0 21 BR1 22 ASK_NFSK 23 CDEM 24 DATA_OUT GND 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary TEST2 1 18 TEST1 2 17 CLK_OUT 3 16 CLK_OUT_CTRL1 4 15 CLK_OUT_CTRL0 5 14 ENABLE Function Test pin, during operation at GND Test pin, during operation at GND Output to clock a connected microcontroller ...

  • Page 4

    ... Figure 1-3. ATA5745/ATA5746 [Preliminary] 4 Block Diagram ASK/FSK CDEM Demo- dulator IF Amp SENSE SENSE_CTRL IF Filter GND LPF DVCC IF Amp LPF LNA_IN LNA LNA_GND ASK VS3V_AVCC Power Supply VS5V FSK ASK/FSK ASK_NFSK Control Data DATA_OUT Slicer BR0 BR1 Standby RX Logic Control CLK_OUT_CTRL1 XTO CLK_OUT_CTRL0 Div ...

  • Page 5

    ... RKE and TPM systems. A benefit of the integrated receive filter is that no external components needed. At 315 MHz, the ATA5745 receiver (433.92 MHz for the ATA5746 receiver) has a typical system noise figure of 6.0 dB (7.0 dB), a system I1dBCP of –31 dBm (–30 dBm), and a system IIP3 of – ...

  • Page 6

    ... MHz and 433.92 MHz. These losses can be estimated when calculating the parallel equivalent resistance of the inductor with loss Figure 2-1. Table 2-2. ATA5745/ATA5746 [Preliminary] 6 Table 2-1. The highest sensitivity is achieved with power matching Measured Input Impedances of the LNA_IN Pin f [MHz] ...

  • Page 7

    ... IF-filter bandwidth of the receiver. page 8 Figure 2-4 9.6 Kbits/s, ±38 kHz, Manchester versus the frequency offset between transmitter and receiver at T amb 3.0V and 3.3V. 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] BR_Range_0 BR_Range_1 2.5 Kbits/s 5 Kbits/s –108 dBm –107 dBm –107 dBm – ...

  • Page 8

    ... ATA5745/ATA5746 [Preliminary] 8 Measured Sensitivity (315 MHz, ASK, 2.4 Kbits/s, Manchester) Versus Fre- quency Offset Input Sensitivity (dBm) at BER < 1e-3, ATA5746, ASK, 2.4 Kbits/s (Manchester), -300 -200 -100 delta RF (kHz) at 315 MHz Measured Sensitivity (315 MHz, ASK, 9.6 Kbits/s, Manchester) Versus Fre- quency Offset Input Sensitivity (dBm) at BER < ...

  • Page 9

    ... ATA5745/ATA5746 [Preliminary] Measured Sensitivity (315 MHz, FSK, 2.4 Kbits/s, ±38 kHz, Manchester) Versus Frequency Offset Input Sensitivity (dBm) at BER < 1e-3, ATA5746, FSK, 2.4 Kbits/s (Manchester), BR0 -112.00 -111.00 -110.00 -109.00 -108 ...

  • Page 10

    ... This system calculation is based on worst-case tolerances of all the components; this leads in practice to a system with margin. For a 433.92 MHz TPM system using ATA5757 as transmitter and ATA5745 as receiver, the same calculation must be done, but since the RF frequency is higher, every ppm of crystal toler- ances results in higher frequency offset and either the system must have lower tolerances or a lower margin at this frequency ...

  • Page 11

    ... BER is higher than 10 The measurements were done at the 50 input shown –102 dBm + 67.5 dBC = –34.5 dBm. Figure 2-6. 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] shows the typical supply current of the receiver in Active mode versus supply voltage Measured Current in Active Mode ASK 2. – ...

  • Page 12

    ... Figure 2-7. Figure 2-8. Table 2-8 cies. Note that sometimes the blocking is measured relative to the sensitivity level 104 dBm (denoted dBS), instead of the carrier –102 dBm (denoted dBC) Table 2-8. ATA5745/ATA5746 [Preliminary] 12 Narrow-band 3-dB Blocking Characteristic at 315 MHz 80.0 70.0 60.0 50 ...

  • Page 13

    ... IF filter. Hence, the demod- ulator, data filter, and data slicer are important. The data filter of the ATA5745/ATA5746 functions also as a quasi-peak detector. This results in a good suppression of above mentioned disturbers and exhibits a good carrier-to-noise perfor- mance ...

  • Page 14

    ... The divided frequency is compared to f current output of the phase frequency detector is connected to the fully integrated loop filter, and thereby generates the control voltage for the VCO. By means of that configuration, the VCO is ...

  • Page 15

    ... High if the amplitude is large enough; this activates the CLK_OUT output enabled via the pins CLK_OUT_CTRL0 and CLK_OUT_CTRL1. Note that the necessary conditions of the DVCC voltage also have to be fulfilled recommended to use a crystal with 1 2.2 pF. 0 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Crystal Equivalent Circuit XTAL fF ...

  • Page 16

    ... Lower values ( fF) can also be used, with only little influence on pulling. m XTO Block Diagram XTAL1 XTAL2 CLK_OUT_CTRL0 and the f XTO RF Calculation Frequency [MHz] 433.92 (ATA5745) 315.0 (ATA5746) CLK_OUT_CTRL1 CLK_OUT f FXTO Divider /3, /6, /12 Amplitude Detector Divider f /16 DCLK is shown in Table 3-1. f ...

  • Page 17

    ... Start-up time of the RX signal path The start-up time and the debounce characteristic depend on the selected bit rate range (BR_Range) which is defined by pins BR0 and BR1. The clock cycle T lowing formulas for further reference: BR_Range 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Setting of f CLK_OUT CLK_OUT_CTRL0 0 0 ...

  • Page 18

    ... RSSI level varies during the transmission. The RS flip-flop can be set back, and thus the receiver switched back to reduced sensitivity, by generating a pos- itive pulse on pin ASK_NFSK (see sensitivity follows the same way. ATA5745/ATA5746 [Preliminary determined by the value of the external resistor R Figure 10-1 on page ...

  • Page 19

    ... Figure 4-1. Figure 4-2. 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Reduced Sensitivity Active ENABLE ASK_NFSK SENSE_CTRL RX V Th_red RSSI t t Startup_PLL Startup_Sig_Proc DATA_OUT Restart Reduced Sensitivity ENABLE ASK_NFSK SENSE_CTRL RX V Th_red RSSI t Startup_Sig_Proc DATA_OUT 19 ...

  • Page 20

    ... Figure 5-1. VS3V_AVCC The supply voltage range of the ATA5745/ATA5746 is 2.7V to 3.3V or 4.5V to 5.5V. Pin VS3V_AVCC is the supply voltage input for the range 2.7V to 3.3V, and is used in battery applications using a single lithium 3V cell. Pin VS5V is the voltage input for the range 4.5V to 5.5V (car applications) in this case the voltage regulator V_REG regulates VS3V_AVCC to typi- cally 3.0V. If the voltage regulator is active, a blocking capacitor of 2.2 µ ...

  • Page 21

    ... During T circuit starts up (T ready to receive. The duration of the start-up sequence depends on the selected bit rate range. Figure 5-3. Active Mode CLK_OUT ENABLE RX DATA_OUT I Standby Standby Mode 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Standby Mode RX ENABLE XTO_Startup Active Mode RX ENABLE 1 1 the PLL is enabled and starts up. If the PLL is locked, the signal processing Startup_PLL ) ...

  • Page 22

    ... Table 5-4. BR1 Table 5-5. ASK_NFSK ATA5745/ATA5746 [Preliminary] 22 Start-up Time ATA5745 (433.92 MHz) BR0 T T Startup_PLL Startup_Sig_Proc 0 1 261 µ Modulation Scheme RF at Pin LNA_IN IN f FSK_H 0 f FSK_L f on ASK 1 f off ASK ATA5746 (315 MHz) T Startup_PLL 1096 µs 644 µs 269 µ ...

  • Page 23

    ... To ensure an accurate settling of the data filter during the start-up period ( time T of the data signal (preamble) must be inside the given limits during this period. EE 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] 25). Each BR_Range is defined by a minimum edge-to-edge time. To maintain full sen- Minimum Edge-to-edge Recommended Bit Rate Time Period T ...

  • Page 24

    ... Figure 6-1. Examples of Supported Modulation Formats MAN: Logic 0 PWM: Logic 0 VPWM: On Transition Low to High On Transition High to Low PPM: Logic 0 NRZ: Logic 0 Figure 6-2. Supported Header and Blanking Periods Preamble ATA5745/ATA5746 [Preliminary Logic Logic 1 Logic Logic Logic Logic 1 Header Data Burst Guard Time ...

  • Page 25

    ... ENABLE RX BR1 BR0 ASK_NFSK DATA_OUT Data valid BR0 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] ) depends on the bit rate range being selected (not current bit Startup_Sig_Proc Table 5-4 on page 22. This response time is specified for applications , the level on pin DATA_OUT is low. T Startup_Sig_Proc Data valid BR3 ...

  • Page 26

    ... The polling period must be controlled by the connected microcontroller via the pins ENABLE and RX. The polling current can be calculated as follows: I Polling (T Bitcheck T Polling_Period T Startup_PLL T Startup_Sig_Proc T Bitcheck T Polling_Period I Startup_PLL I : Active I : Standby Example:- ATA5745/ATA5746 [Preliminary] 26 Polling Cycle RX I Active I Standby Signal_Bitrate (average) Bitcheck T Startup_Sig_Proc T (Startup RF-PLL) Startup_PLL = ( Startup_PLL Polling_Period / ...

  • Page 27

    ... Application Figure 9-1. 3V Application output output output output input output VSS VCC Note: 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary TEST2 TEST1 ATA5745/ CLK_OUT ATA5746 CLK_OUT_CTRL1 CLK_OUT_CTRL0 ENABLE 2.7V to 3.3V CC Paddle (backplane) must be connected to GND TEST3 RSSI SENSE_CTRL SENSE RF 2 LNA_IN 68 nH/36 nH LNA_GND 315 MHz/433 ...

  • Page 28

    ... Application Figure 10-1. 5V Application With Reduced/Full Sensitivity output output output output output input output VSS VCC Note: ATA5745/ATA5746 [Preliminary TEST2 TEST1 ATA5745/ CLK_OUT ATA5746 CLK_OUT_CTRL1 CLK_OUT_CTRL0 ENABLE 4.5V to 5.5V CC Paddle (backplane) must be connected to GND TEST3 RSSI SENSE_CTRL R Sense SENSE 2.2 pF ...

  • Page 29

    ... System start-up time XTAL Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to Table 2-2 on page 6 nent values as in 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] Symbol stg T amb V S ...

  • Page 30

    ... Bit rate 2.4 Kbits/s BR0 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to Table 2-2 on page 6 nent values as in ATA5745/ATA5746 [Preliminary –40°C to +105°C, V amb VS3V_AVCC = 25° ...

  • Page 31

    ... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to Table 2-2 on page 6 nent values as in 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] = –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 315 MHz unless otherwise specified ...

  • Page 32

    ... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to Table 2-2 on page 6 nent values as in ATA5745/ATA5746 [Preliminary –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 315 MHz unless otherwise specified. Details about current ...

  • Page 33

    ... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to Table 2-2 on page 6 nent values as in 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] = –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 315 MHz unless otherwise specified ...

  • Page 34

    ... CLK_OUT_CTRL0 = 1 --> division ratio = 12 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to Table 2-2 on page 6 nent values as in ATA5745/ATA5746 [Preliminary –40°C to +105°C, V amb VS3V_AVCC = 25° ...

  • Page 35

    ... Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: 1. Pin numbers in parenthesis were measured with RF_IN matched to 50 according to Table 2-2 on page 6 nent values as in 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] = –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 315 MHz unless otherwise specified ...

  • Page 36

    ... VS3V_AVCC Current in Active mode V VS5V 7.6 FSK CLK disabled SENSE_CTRL = 0 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5745/ATA5746 [Preliminary –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 433.92 MHz unless otherwise specified. Details about current VS5V ...

  • Page 37

    ... Current in Active 8.6 CLK disabled mode FSK SENSE_CTRL = 0 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] = –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 433.92 MHz unless otherwise specified. Details about current ...

  • Page 38

    ... BR_Range_1 10.5 for full sensitivity in BR_Range_2 Active mode BR_Range_3 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5745/ATA5746 [Preliminary –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 433.92 MHz unless otherwise specified. Details about current ...

  • Page 39

    ... High level input VS5V voltage V S 4.5V to 5.5V *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] = –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 433.92 MHz unless otherwise specified. Details about current ...

  • Page 40

    ... TEST2 output always be connected directly to GND TEST3 input must 11.11 TEST3 input always be connected directly to GND *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5745/ATA5746 [Preliminary –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 433.92 MHz unless otherwise specified. Details about current ...

  • Page 41

    ... Saturation voltage V S high 4.5V to 5.5V I DATA_OUT *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] = –40°C to +105°C, V amb VS3V_AVCC = 25°C, and f = 433.92 MHz unless otherwise specified. Details about current VS5V ...

  • Page 42

    ... ATA5745-PXQW ATA5746-PXQW 19. Package Information Package: QFN Exposed pad 3.6 x 3.6 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances ±0. Drawing-No.: 6.543-5122.01-4 Issue: 1; 15.11.05 ATA5745/ATA5746 [Preliminary] 42 Package MOQ QFN24 1500 pcs QFN24 1500 pcs QFN24 6000 pcs QFN24 6000 pcs 0.9 ± ...

  • Page 43

    ... Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4596B-RKE-06/07 4596B–RKE–06/07 ATA5745/ATA5746 [Preliminary] History Put datasheet in a new template Section 13 “Electrical Characteristics: General” numbers 2.1, 2.2 and 3.1 on pages changed Section 14 “ ...

  • Page 44

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...