ATAB5429-9-WB Atmel, ATAB5429-9-WB Datasheet - Page 53

• Manufacturer Part Number: ATAB5429-9-WB
• Description: KIT DEMO 915MHZ BLACKBIRD
• Manufacturer: Atmel
• Type: Transceiver, UHFr

Specifications of ATAB5429-9-WB

• Frequency: 915MHz
• Maximum Frequency: 915 MHz
• Output Power: 0 dBm to 10 dBm
• Supply Voltage (max): 6 V
• Supply Voltage (min): 3 V
• Supply Current: 21 mA
• Maximum Operating Temperature: + 85 C
• Board Size: 2 in x 3.5 in
• Minimum Operating Temperature: - 40 C
• Product: RF Modules
• For Use With/related Products: ATA5429
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATAB-5429-9-WB; ATAB-5429-9-WB

9.1.2
9.1.3
4841D–WIRE–10/07
Sleep Mode
Start-up Mode
To save current it is recommended that CLK and V
does not include the current of the Microcontroller_Interface, I
device connected to pin VSOUT (for example, microcontroller). If CLK and/or VSOUT is enabled
during RX polling mode the current consumption is calculated as follows:
During T
nal. To guarantee the reception of a transmitted command, the transmitter must start the
telegram with an adequate preburst. The required length of the preburst, T
the polling parameters T
the actual bit rate and the number of bits (N
The length of period T
factor X
calculated to be:
In US and European applications, the maximum value of T
(which is done by setting the bit X
1.2 ms in that case. The sleep time can be extended to about 300 ms by setting X
(which is done by setting X
9.6 ms.
During T
circuit starts up (T
ready to receive.
I
T
T
S_Poll
Preburst
Sleep
=
=
Sleep
I
Sleep
Sleep
Startup_PLL
P
T
+
Sleep
I
, T
defined by the bit X
VSINT
+
Startup_PLL
1024
T
+
Startup_PLL
the PLL is enabled and starts up. If the PLL is locked, the signal processing
Startup_Sig_Proc
I
EXT
Sleep
ATA5423/ATA5425/ATA5428/ATA5429
T
Sleep
DCLK
and T
is defined by the 5-bit word sleep in control register 4, the extension
+
, T
Sleep
T
Startup_Sig_Proc
Startup_Sig_Proc
Startup_PLL
X
). After the start-up time all circuits are in stable condition and
Sleep
Sleep
in control register 4 to “1”), the time resolution is then about
Sleep
in control register 4, and the basic clock cycle T
in control register 4 to “0”). The time resolution is about
, T
Startup_Sig_Proc
, the transceiver is not sensitive to a transmitter sig-
+
Bit-check
T
Bit_check
VSOUT
) to be tested.
and T
be disabled during RX polling mode. I
Sleep
Bit-check
VSINT
is about 38 ms if X
, or the current of an external
. Thus, T
Preburst
Bit-check
Sleep
, depends on
depends on
is set to 1
DCLK
Sleep
. It is
to 8
53
P