MICRF005BM Micrel Inc, MICRF005BM Datasheet - Page 6

• Manufacturer Part Number: MICRF005BM
• Description: IC RECEIVER UHF 900MHZ 14SOIC
• Manufacturer: Micrel Inc

Specifications of MICRF005BM

• Frequency: 800MHz ~ 1GHz
• Sensitivity: -84dBm
• Data Rate - Maximum: 115 kbps
• Modulation Or Protocol: OOK
• Applications: Wireless Game Controllers
• Current - Receiving: 10mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: Automatic Tuning
• Voltage - Supply: 4.75 V ~ 5.3 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• No. Of Driver/receivers: 0/1
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5.5V
• Current Rating: 18.5mA
• Data Rate Max: 115Kbps
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Supply Current: 10mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant

MICRF005
duty-cycled operation. The actual tolerable leakage will be
application dependent. Clearly, leakage performance is less
critical when the device off-time is low (milliseconds) and
more critical when the off-time is high (seconds).
To further enhance duty-cycled operation of the IC, the AGC
push and pull currents are increased for a fixed time immedi-
ately after the device is taken out of shutdown mode (turned-
on). This compensates for AGC capacitor voltage droop
while the IC is in shutdown mode, reduces the time to restore
the correct AGC voltage, and therefore extends maximum
achievable duty ratios. Push-pull currents are increased by
45 times their nominal values. The fixed time period is based
on the reference oscillator frequency f
14.3359MHz, and varies inversely as f
Transmit / Standby Function
The transmit/receive function is controlled by the logic state
of T/R. T/R is internally tied to V
or in the low state, the MICRF005 functions in its normal
receive operating mode. The T/R pin may be pulled high to
Vdd, this will place the receiver in a “stand-by” operating
mode. This mode is intended for use during transmit cycles
in transceiver applications where the receiver is co-located
with a transmitter. In this “transmit” mode, the receiver
oscillator remains active but the AGC function is disabled and
the CAGC pin is high impedance to hold the AGC capacitor
voltage. This function enables the MICRF005 to immediately
resume receive operation after a transmit cycle.
Shutdown Function
The shutdown function is controlled by a logic state applied
to the SHUT pin. When V
low-power standby mode, consuming less than 1 A. This pin
is pulled high internally. It must be externally pulled low to
enable the receiver.
Reference Oscillator
All timing and tuning operations on the MICRF005 are de-
rived from the internal Colpitts reference oscillator. Timing
and tuning is controlled through the REFOSC pin in one of two
ways:
The second approach is attractive for lowering system cost
further if an accurate reference signal exists elsewhere in the
system, for example, a reference clock from a crystal-con-
trolled microprocessor. An externally applied signal should
be ac-coupled and resistively-attenuated, or otherwise lim-
ited, to approximately 0.5Vpp. The specific reference fre-
quency required is related to the system transmit frequency.
I/O Pin Interface Circuitry
Interface circuitry for the various I/O pins of the MICRF005
are diagrammed in Figures 1 through 6. The ESD protection
diodes at all input and output pins are not shown. Integrated
into an actual design application with the best results pos-
sible.
MICRF005
1. Connect a crystal
2. Drive this pin with an external timing signal
SHUT
is high, the device goes into
SS
. When T/R is open circuit
T
T
varies.
, [tbd]ms for f
T
=
6
CTH Pin
Figure 2 illustrates the CTH-pin interface circuit. The CTH pin
is driven from a P-channel MOSFET source-follower with
approximately 10 A of bias. Transmission gates TG1 and
TG2 isolate the 6.9pF capacitor. Internal control signals
PHI1/PHI2 are related in a manner such that the impedance
across the transmission gates looks like a “resistance” of
approximately 100k . The dc potential at the CTH pin is
approximately 1.6V
CAGC Pin
Figure 3 illustrates the CAGC pin interface circuit. The AGC
control voltage is developed as an integrated current into a
capacitor C
the decay current is a 1/10th scaling of this, nominally 1.5 A,
making the attack/decay timeconstant ratio a fixed 10:1.
Signal gain of the RF/IF strip inside the IC diminishes as the
voltage at CAGC decreases. Modification of the attack/decay
ratio is possible by adding resistance from the CAGC pin to
either V
Both the push and pull current sources are disabled during
shutdown, which maintains the voltage across C
improves recovery time in duty-cycled applications. To fur-
ther improve duty-cycle recovery, both push and pull currents
are increased by 45 times for approximately 10ms after
release of the SHUT pin. This allows rapid recovery of any
voltage droop on C
DDBB
Demodulator
AGC
Timout
2.85Vdc
or V
Signal
Compa-
rator
. The attack current is nominally 15 A, while
SSBB
AGC
Figure 3. C
Figure 2. C
VDDBB
VSSBB
, as desired.
1.5µA
15µA
while in shutdown.
PHI2B
PHI2
VDDBB
VSSBB
AGC
VSSBB
TH
6.9pF
Pin
67.5µA
675µA
Pin
PHI1B
PHI1
CAGC
October 2001
CTH
AGC
Micrel
, and