SX1441I077TRLF Semtech, SX1441I077TRLF Datasheet

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... This product has been designed for ultra low power consumption and low cost solutions. By combining the SX1441 with a low power 2.4 GHz radio device such as the XE1413, from Semtech, an ultra low power Bluetooth wireless headset consuming less than 23mW @1.8V (HV3) can be built. ...

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... Block diagram ......................................................................................................................................33 3.8.4 Debounce mode ..................................................................................................................................33 3.8.5 Pull-ups/Snap-to-rail ............................................................................................................................33 3.8.6 Interrupt sources..................................................................................................................................34 3.8.7 Event sources ......................................................................................................................................34 3.8.8 Clock sources ......................................................................................................................................34 3.8.9 Reset sources......................................................................................................................................35 3.9 Digital input/output port PB[7:0] ................................................................................................................35 3.9.1 Features...............................................................................................................................................35 © Semtech 2006 Table of Contents 2 Data Sheet SX1441 – Bluetooth® 1.2 SoC www.semtech.com ...

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... Register map .......................................................................................................................................70 3.15.3 Pins mapping .......................................................................................................................................71 3.15.4 Configuration .......................................................................................................................................73 3.15.5 Configuration Examples ......................................................................................................................74 3.16 Development / Debug On Chip.................................................................................................................74 4 Electrical Specifications....................................................................................................................................75 4.1 Absolute Maximum Ratings ......................................................................................................................75 4.2 Recommended Operating Conditions ......................................................................................................75 © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC TM Commands” ............................................................60 3 Data Sheet www.semtech.com ...

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... MHz crystal oscillator ................................................................77 5 Application Schematics – Bluetooth Headset ..................................................................................................78 6 Packaging Information – 72-pin LFBGA...........................................................................................................80 7 Soldering Reflow Profile ...................................................................................................................................81 8 Reference Documents......................................................................................................................................81 9 Notice, Trademarks ..........................................................................................................................................81 © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC 4 Data Sheet www.semtech.com ...

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... Bluetooth technology, with low risk and a short development time. The core of the SX1441 is the Semtech ROM-based Bluetooth sequencer combined with an embedded 8-bit RISC microcontroller and several standard peripherals such as GPIO, high speed UART, audio CODEC, and a power management unit ...

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... A1 TP0 A2 TP1 A3 TP2 Connect to A4 PB[1] A5 PB[3] A6 PB[5] / UA_RTS A7 PB[7] / UA_RX A8 MOSI A9 MISO A10 SCK B1 NRESET B2 VSS_DIG © Semtech 2006 Bottom view 7mm Figure 2 - LFBGA72, bottom view Type/ Reset Do not Do not connect connect Do not Do not connect connect Connect to ground ground ...

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... PA[2] E10 PA[1] F1 VREF F2 VDD_M F5 DBG[1] F6 DBG[3] F9 PA[4] F10 PA[3] G1 VSS_M G2 VREGD © Semtech 2006 Type/ Reset General purpose port B I General purpose port B I General purpose port B I/O UART CTS handshaking General purpose port B I/O UART transmit signal P P digital pads ground ...

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... DOC_SDIO K1 VSS_PA K2 TP4 K3 SLW_CLK_IN K4 RX_DATA K5 SPI_EN_BAR K6 TX_EN K7 SYNC_DETECT K8 RX_EN K9 TX_DATA K10 DOC_SCK A : Analog u : Internal pull-up © Semtech 2006 Type/ Reset Debug Interface PCM fsync Debug Interface PCM data General purpose port General purpose port Power amplifier positive P P Power amplifier supply P P ...

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... Reset NRESET Controller Interrupt Controller Counter/ Timer SYS_CLOCK_IN Clock Controller SLW_CLOCK_IN RC Oscillator TP[4 :0] DOC_SCK, DoC DOC_SDIO DBG[7 :0] © Semtech 2006 Program Memory (ROM / RAM) CoolRISC 816 RISC CPU BT HCI uart UART bus pcm bus Codec GPIO PB Application UART GPI PA SPI Power ...

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... ACL (data) links and one SCO (audio) link in a point-to-point, piconet, or scatternet network configuration. The debug-on-chip (DoC) peripheral interfaces the chip with the software debugger. © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC ® 816 8-bit RISC processor is ...

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... The 16 8-bit registers enable the use compiler. The complete CPU hardware and software description is given in the document “CoolRISC 816, 8-bit Microprocesor Core, Hardware and Software Reference Manual”, version 4.5 which can be found on the Semtech website (http://www.semtech.com). μF μF 0xBFFF ...

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... Pos RegPmgtVrega r/w 7 DefaultVrega rw 4 EnableVrega rw 3:0 TuneVrega rw © Semtech 2006 Address range 0x0010 to 0x001F 0x0020 to 0x0027 0x0028 to 0x002D 0x0030 to 0x0037 0x0038 to 0x003B 0x003C to 0x003F 0x0040 to 0x0047 0x0048 to 0x004C 0x0050 to 0x0057 0x0058 to 0x005F 0x0068 to 0x006F 0x007C to 0x007D 0x0080 to 0x009F 0x00E0 to 0x00FF ...

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... VREGD outputs 1.8V and the pin VREGA is floating. • AUDIO mode: all blocks are powered entered upon request from the application. In the AUDIO mode, the pins VREGA and VREGD output 1.8V. WAKEUP OFF Software control (for ex. Timeout or button) © Semtech 2006 Reset Function 0 value of the wakeup pin 00 reserved 1 ...

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... VDDIO is the power supply for the radio interface. If the radio chip is powered by VREGD, then VDDIO should be connected to VREGD as well. VDDIO_DIG is the power supply for most of the digital pads. Depending on the application, it may be connected to VREGD, VDD_M, or any other power supply which fulfills the specifications. © Semtech 2006 VDD_M VREF ...

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... Equation 1. For cThe start up time of the end-of-life circuit VDDBAT EOLres V EOLThresho Equation 1 - Threshold voltage of the EOL comparator © Semtech 2006 for best performances. VREGD has to be connected to an VDD_M to insure the stability and the performance of the voltage regulator. VREGA . VDD_PA can be connected to VREGD. VREF ...

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... EnableBusError rw 4 EnableResetWD rw 3 Pos RegSysWd r/w 7 3:0 WDKey rw © Semtech 2006 Min Typ Max 0.710 0.725 0.740 0.710 2.34 100 20 Table 10 - End-of-life analog specifications Address (Hex) 0x0010 0x0014 Table 11 - Reset controller registers Reset Function 0 Bit reserved for test purpose ...

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... Only writing 0x0a followed by 0x03 will clear the watchdog. If some other writing is done in and between, in RegSysWd, then the watchdog will not be cleared. The status of the watchdog may be checked by reading the register RegSysWd. The watchdog is a four bit counter with a range The reset is generated when the counter reaches the value 8. © Semtech 2006 VDD_M POR_VDD_M VDD_DIG POR_VDD_DIG Figure 9 – ...

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... Two divider chains: high-prescaler (8 bits) and low-prescaler (15 bits). • CPU clock disabled in halt mode. 3.5.2 Register Map Name RegSysClock RegSysMisc RegSysPre0 RegSysRcTrim1 RegSysRcTrim2 Table 15 – Clock distribution registers addresses Pos RegSysClock r/w © Semtech 2006 V rstT t rise Description Min Start Voltage 0.8 Drop Voltage ...

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... Pos RegSysRcTrim2 r/w 7 5:4 RCCoarseLSB rw © Semtech 2006 Reset Function Low Speed Clock Selected (generally: an external 32kHz clock crystal High Speed Clock Selected (the nature of the clock selected will depend on the EnableSysClk bit value Force the SLW_CLOCK_IN clock as the low prescaler input when a low speed clock is available (i ...

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... The RC clock is always selected after power- negative pulse on the NRESET pin. The CPU clock selection is done with the register RegSysClock according to the Table 22. Switching from one clock source to another is glitch free. See also Figure 11, Figure 12, and Figure 13. © Semtech 2006 0000 RC fine adjustment ...

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... RegSysMisc Description When OutputCk32kHz is 1, the ck32kHz clock is output of the port B PB[3]. The CPU clock is output on the port B PB[2] when the bit OutputCkCpu is 1. 3.5.8 Prescalers The Figure 11 describes the overall structure of the prescaler. © Semtech 2006 Clock Targets CpuCk CpuSel = 0 CpuSel = 1 ...

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... Personal Area Network RC ckRC Oscillator SYS_CLOCK_IN EnableSysClock SLW_CLOCK_IN (EnableRC) OR (EnableSysClock) © Semtech 2006 0 1 High Prescaler Low Prescaler 1 0 CpuSel Figure 11 - Prescaler Unit block diagram 22 Data Sheet SX1441 – Bluetooth® 1.2 SoC ckRCext ckRCext/2 … ckRCext/256 SelLowPresIn RCDivFactor RCCoarse RCFine ck32kHz … ...

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... EnableSlwClock is set to 1. The bit ColdSlwClock value indicate that the SLW_CLOCK_IN is in its starting phase. It automatically enters this phase when the bit EnableSlwClock is set to 1. During this phase, SLW_CLOCK_IN is not available. It becomes available after 32’768 cycles, when the bit ColdSlwClock returns to 0. © Semtech 2006 ÷ 2 ckRCext/2 ÷ 2 ckRCext/4 ÷ ...

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... Semtech 2006 SelLowPresIn 1 Ck32kHz 0 ÷ 2 Ck16kHz ÷ 2 Ck8kHz ÷ 2 Ck4kHz ÷ 2 Ck2kHz ÷ 2 Ck1kHz ÷ 2 Ck512Hz ÷ 2 Ck256Hz Figure 13 - Low prescaler block diagram RCDivFactor & ...

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... Semtech 2006 SX1441 – Bluetooth® 1.2 SoC RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x0510]hex [0x0519]hex [0x0520]hex [0x0527]hex [0x0530]hex [0x0535]hex [0x0540]hex [0x0544]hex [0x0550]hex [0x0552]hex ...

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... Low prescaler output Peripherals ck32kHz application UART, Bluetooth sequencer UART, counter/timer, port PA debouncer ck2kHz counter/timer ck1kHz counter/timer, port PA debouncer © Semtech 2006 RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x06c8]hex [0x06d0]hex [0x06d6]hex [0x06e0]hex ...

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... ReqIrqIrq Pos RegIrqHig r 128Hz rc1 5 Spi rc1 4 CntA rc1 3 CntC rc1 © Semtech 2006 Table 25 - Low prescaler outputs usage RC Application Oscillator Processor Bluetooth Sequencer CODEC Address (Hex) 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 0x0047 Table 26 - Interrupt controller register map Reset ...

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... EnUartTx rc1 6 EnUartRx rc1 5 EnPa5 rc1 4 EnPa4 rc1 3 En1Hz rc1 © Semtech 2006 Reset Function 0 interrupt from Codec 0 interrupt from Bluetooth Sequencer UART transmitter 0 interrupt from Bluetooth Sequencer UART receiver Table 27 - RegIrqHigh register Reset Function 0 interrupt from application UART transmitter 0 interrupt from application UART receiver ...

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... Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number of the highest priority set (its value is 0xFF when no interrupt is memorized). RegIrqIrq indicates the priority level of the current interrupts. © Semtech 2006 Reset Function 0 ...

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... EvnPriority r Pos RegEvnEvn r/w 7 EvnHigh r 0 EvnLow r © Semtech 2006 Address (Hex) 0x003C 0x003D 0x003E 0x003F Table 35 - Event controller registers Reset Function 0 event from counter A (high priority) 0 event from counter C (high priority) 0 reserved 0 event from port PA[1] (high priority) ...

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... Pos RegPAIn r/w 7:0 PAIn r Pos RegPADebounce r/w 7:0 PADebounce rw Pos RegPAEdge r/w 7:0 PAEdge rw © Semtech 2006 Address (Hex) 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 Table registers Reset Function xxxxxxxx value of pads PA[7:0] Table 41 - RegPAIn register Reset Function ...

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... DebounceSelect rw Pos RegPASnapToRail r/w 7:0 SnapToRail rw © Semtech 2006 Table 43 - RegPAEdge register Reset Function 11111111 1 = pull-up enabled (for each corresponding PA pad pull-up disabled (for each corresponding PA pad) Table 44 - RegPAPullup register Reset Function 00000000 for each corresponding PA pad: bit 0 of reset configuration (see 3.8.9) ...

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... It also reduces the power consumption with respect to a classic pull-up since it selects the pull-up or pull-down resistor that matches the detected input state. The state of input pin is summarized in Table 50. © Semtech 2006 Port A 8 ...

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... Pins PA[0] and PA[1] are also available as events on the event controller. 3.8.8 Clock Sources PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the counter/timer/PWM peripherals. © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC Last externally forced PA[i] value X ...

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... Name RegPBOut RegPBIn RegPBDir RegPBOpen RegPBPullup Pos RegPBout r/w 7:0 PBOut rw Pos RegPBIn r/w 7:0 PBIn r © Semtech 2006 PARes0[ Table 51 - PAReset generation Address (Hex) 0x0028 0x0029 0x002A 0x002B 0x002C Table 52 - port PB registers Reset Function 00000000 port output value Table 53 - RegPBOut register ...

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... RegPBOut[3]. However, RegPBDir[3] must be set to 1. The frequency and duty cycle of the clock signal are given in Figure 16. 1/f Similarly, If bit 0 is set in RegSysMisc, the CPU clock is output on PB[2] as described on Figure 17. This overrides the value contained in RegPBOut[2]. However, RegPBDir[2] must be set to 1. © Semtech 2006 Reset Function 00000000 for each corresponding PB pad: ...

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... Rising, falling or both edge of capture signal (except for ck32k, only rising edge) • PA[3:0] can be used as clock inputs (debounced or direct, frequency divided not) • bits PWM bits PWM • PWM resolution of 8, 10, 12 bits • Complex mode combinations are possible © Semtech 2006 1/f1 1/f2 Figure 17 - CPU output clock timing ckRCext ...

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... CntACkSel rw Pos RegCntConfig1 r/w 7 CntDDownUp rw 6 CntCDownUp rw 5 CntBDownUp rw 4 CntADownUp rw 3 CascadeCD rw © Semtech 2006 Address (Hex) 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F Table 60 - Counter Registers Reset Function (1) 00000000 counter A Table 61 - RegCntA register Reset Function (1) 00000000 counter B ...

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... PWM and B as counter PWM and B as captured counter. When counters C and D are not cascaded, both can be used either as counters or counter C as PWM and counter D as counter. Counters are enabled by RegCntOn. When counters are cascaded, the bit CntBEnable controls the counter and CntDEnable controls the counter © Semtech 2006 Reset Function 0 ...

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... Mode Selection Each counter can be configured in the following modes: Counter Capture PWM Captured PWM The counter mode is set by writing the registers RegCntConfig1 and RegCntConfig2. © Semtech 2006 Counter B Counter C ck1kHz low prescaler output ck32kHz low prescaler output PA[1] PA[2] Table 69 - Counter clock selection ...

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... A and C. When in upcount mode, the counter will start incrementing from zero up to the target value which has been written in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is © Semtech 2006 Counter A Counter B Counter A IRQ ...

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... Counters in PWM mode count down or up, according to the RegCntConfig1[7:4] bit setting. No interrupts and events are generated by the counters which are in this mode. Counters count circularly: they restart at zero or at the maximal value (0xFF when not cascaded or 0xFFFF when cascaded) when respectively an overflow or an underflow condition occurs. © Semtech 2006 down counting 3 2 ...

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... The capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or from the external PA[2] or PA[3] ports. Both counters use the same capture condition. © Semtech 2006 . PWM Resolution ...

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... In this case, the processor should read the shadow register associated to a counter only if the interruption related to this counter has been detected. An edge is detected on the capture signals only if the minimal pulse widths of these signals in the low and high states are higher than a period of the counter clock source. © Semtech 2006 RegCntConfig2[5:4] Selected ...

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... SpiMaster rw 4 SpiEnable rw 3 ClockPhase rw 2 ClockPolarity rw 1:0 BaudRate rw © Semtech 2006 Address (Hex) 0x0068 0x0069 0x006A 0x006B 0x006C 0x006D 0x006E Table 74 - SPI registers Reset Function clear control counters 1 In master mode: drives the NSS[0] pin. It must be set to 0 during byte transfer. ...

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... Pos RegSpiSlvSel r/w 7 MultSlvSel rw 1:0 SlvSelect[1:0] rw © Semtech 2006 Reset Function 00000 reserved 0 Overflow flag. Cleared when written byte has been received and is available in the receive register. This flag is cleared when reading RegSpiDataIn the transmit register is empty and a new transfer can be initiated. The flag is cleared when writing RegSpiDataOut ...

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... SCK signal occurs on the 2 Figure 21 - SPI transmission format with a clock phase equal to 0 The Figure 22 shows the timing diagrams for a SPI transmission with a clock phase equal to 1 (the active state of the serial clock SCK signal occurs on the 1 © Semtech 2006 Boot flash SCK SI ...

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... Byte transfer Wait until the receive buffer is full (SpiRxFull set in RegSpiStatus) Read the received data from RegSpiDataIn Fetch the SPI with the data to be transmitted. The data is written in RegSpiDataOut © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC 48 Data Sheet www.semtech.com ...

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... RegUartFifoCtrl RegUartFifoBaud RegUartFifoTx RegUartFifoTxSta RegUartFifoRx RegUartFifoRxSta RegUartFifoMisc © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC GPIO digital I/O with selectable pull-up digital I/O with selectable pull-up digital I/O with selectable pull-up digital I/O with selectable pull-up digital I/O with selectable pull-up ...

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... UartTxBusy r 0 UartTxFifoEmpty r 7:0 UartTxClear w Pos RegUartFifoRx r/w 7:0 UartRx r © Semtech 2006 Reset Function echo mode selected (UA_RX and UA_TX internally connected echo mode not selected receiver enabled 0 = receiver disabled transmitter enabled 0 = transmitter disabled UA_RX inverted 0 = UA_RX not inverted ...

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... UartFlowCtrl rw 1 3.12.3 Block Diagram The UART is a Universal Asynchronous Receiver Transmitter interface with separated receive and transmit 8-byte FIFO, and fully automatic flow control. Control Registers © Semtech 2006 Reset Function 0 reserved 0 receive FIFO full flag 0 start error flag 0 parity error flag ...

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... UartRcDiv 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 © Semtech 2006 f = ckRCext ⋅ ⋅ 16 factorUart RcSel factorUart Equation 3 – Baudrate vs. ckRCext factorUartRcSel Table 91 - Division factor for UartRcSel factorUartRcDiv 52 Data Sheet SX1441 – Bluetooth® 1.2 SoC ...

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... Writing in RegUartFifoTxSta resets the transmitter block. Data in the FIFO that were not transmitted are lost. The flags in RegUartFifoTxSta are reset. Figure 24 and Figure 25 show an UART transmission. The figures are drawn with a FIFO depth of 2, for simplification, although the FIFO depth is 8. © Semtech 2006 factorUartRcDiv Table 92 - Division factor for UartRcDiv f = ...

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... FIFO depending on RtsLevelMode. Figure 26 shows the timing diagram for a possible reception. In this example, the depth of the FIFO is 4. RTS1 shows the functionality when RtsLevelMode = 0 and RTS2 when RtsLevelMode = 1. The actual depth of the FIFO is 8. © Semtech 2006 start bit0 bit1 ...

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... Jump write the next 8 bytes if the message is not finished End of transmission 3.12.9.2 Transmission with Interrupt Initialize RegUartFifoBaud and RegUartFifoCtrl with the communication parameters (for example 8-bit word length, odd parity, 115200 bauds, enable UART transmission) © Semtech 2006 word1 bit1 bit7 parity stop start ...

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... BtmWlanBusy rw 5 BtmReset rw 4 BtmEnable rw 3 BtmSpiEnBar rw 2 BtmBusy r © Semtech 2006 Address (Hex) 0x007C 0x007D Table 94 – Bluetooth Sequencer registers Reset Function 00 unused colocated WLAN is currently receiving WLAN activity currently active Reset Bluetooth Sequencer 0 = Enable Bluetooth Sequencer (see also bit 4) ...

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... All Bluetooth specific commands are usually embedded into abstraction layers by the upper layers of the Bluetooth stack, so that the programmer only deals with common services (e.g. serial port emulation, etc …). Full Bluetooth stacks from various vendors have been successfully ported to the SX1441. © Semtech 2006 Reset Function ...

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... Link Controller Feature SCO links eSCO links ACL links Packet formatting Control packets (ID, NULL, POLL, FHS) Voice packets (HV1, HV2, HV3) eSCO packets (EV3, EV4, EV5) Mixed voice-data packets (DV) © Semtech 2006 Application HCI (hosted) CoolRISC 816 TX RTS CTS RX HCI (embedded) Link Manager ...

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... Standard Host Controller Interface (HCI) Commands The table contains all messages understood by the Link Manager of the SX1441. A detailed description of the command and of its parameters can be found in the HCI specification of the Bluetooth Specification [1]. © Semtech 2006 Table 97 – Link controller features Table 98 – Link manager features ...

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... EasyBlue_SetBdAddr 0x3F Parameters Parameter Size Reserved1 1 byte BdAddr 6 bytes Reserved2 11 bytes Status 1 byte © Semtech 2006 TM Commands” OCF Parameters 0x02 Address, Length, Data Table 99 - EasyBlue_WriteReg synopsis Comment address of the register (MSB first) fixed Number of bytes to transfer data 0x00 : command succeed ...

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... Flow control is enabled at all time for the HCI UART. Upon start-up / reset, the HCI UART is configured for 115’200 kbits/s, 8 bits, no parity. 3.13.10 Bluetooth Sequencer Clock Source As shown in paragraph 3.5.9, the Bluetooth sequencer is clocked by SYS_CLOCK_OUT and SLW_CLOCK_OUT. Both must fulfill the Bluetooth specifications. They are usually generated by the radio chip. © Semtech 2006 Location ...

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... RegDmaWrStartAddrH RegDmaWrStartAddrL RegDmaWrStopAddrH RegDmaWrStopAddrL RegDmaCtrl RegCodecDataFlow * reserved RegADCGain * reserved RegCodecPaMute * reserved Pos RegVolCtrl 7 VolCtrlDACMute 1 VolCtrlADCMute 0 VolCtrlEn © Semtech 2006 Address (Hex) 0x0064 0x0065 0x0066 0x0067 0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x00E7 0x00E8 0x00E9 0x00EA 0x00EB 0x00EC 0x00ED 0x00EE 0x00EF ...

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... DACSample[15:8] Pos RegDACSampleL 7:0 DACSample[7:0] Pos RegADCSampleH 7:0 ADCSample[15:8] Pos RegADCSampleL 7:0 ADCSample[7:0] © Semtech 2006 r/w Reset Function rw 00000000 Signed ADC scaling factor. See Description below Table 109 - RegVolCmdADC register r/w Reset Function rw 00000000 Signed DAC scaling factor. See Description below ...

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... DmaWriteStopAddr[15:8] Pos RegDmaWrStopAddrL 7:0 DmaWriteStopAddr[7:0] Pos RegDmaCtrl 7 DmaReadCntLoad 4 DmaWriteCntLoad © Semtech 2006 r/w Reset Function rw 00000000 MSB of the start address of the DMA read channel buffer Table 116 - RegDmaRdStartAddrH register r/w Reset Function rw 00000000 LSB of start address of the DMA read channel ...

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... RegAdcGain 7 PreampDisable 1:0 PreampGain Pos RegCodecPaMute 7 PaMuteP 0 PaMuteN © Semtech 2006 r/w Reset Function channel address counter r 0 set to 1 when the DMA read channel address counter reaches DmaReadStopAddr[15: set to 1 when the DMA write channel address counter reaches DmaWriteStopAddr[15: enable DMA read channel ...

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... RegDmaWrStopAddrH/-L an interrupt to the host processor is generated. The interrupt service routine must stop the DMA access, write new start and stop addresses in RegDmaRdStartAddrH/-L and RegDmaRdStopAddrH RegDmaWrStartAddrH/-L and RegDmaWrStopAddrH/-L, and enable again the read or write channel. If © Semtech 2006 ADC CoolRISC data bus DMA Current & ...

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... Total harmonic distortion (relative to full scale) SNR Signal-to-Noise Ratio Note 1 : Values below are specified at 25degC and for VDD_M > 2.2V unless otherwise specified Note2 : Values marked with asterisks are not production tested and guaranteed by design. © Semtech 2006 Min Typ Max Unit 0 ...

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... Figure 33) at high frequency and whose cyclic ratio is proportional to the amplitude of the audio signal. The PWM switching frequency has to be filtered to limit power consumption and risk of degradation of the speaker. © Semtech 2006 SX1441 Figure 30 - Equivalent schematic for gain calculation Figure 32 - Equivalent schematic for C ...

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... The output filter is a balanced 2-pole filter. Equation 5 gives a raw estimation of the values of the external inductors and capacitors as a function of the speaker impedance Z kHz, as defined by the Bluetooth audio specifications ⋅ 2 Equation 5 – Typical L and C values for the speaker output filter © Semtech 2006 PA_OUTP PA_OUTN PWM bitstream Figure 33 - Power Amplifier (PA) structure VDD_PA L PA_OUTP ...

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... Register Map Name RegDbgDir RegDbgOut RegDbgIn RegDbgMode Pos RegDbgDir r/w 7-0 DbgDir[7:0] rw Pos RegDbgOut r/w 7-0 DbgOut[7:0] rw © Semtech 2006 = 32 Ω as typical values, gives L = 860 μH and μ kHz and max( ( sign ADCScaling abs ADCScaling Address (Hex) 0x0078 0x0079 0x007A 0x007B Table 129 – ...

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... Pins Mapping Pin DBG[7] DBG[6] DBG[5] DBG[4] DBG[3] DBG[2] DBG[1] DBG[0] © Semtech 2006 Reset Function 00000000 DBG[7:0] pad input value. Valid only in GPIO mode Table 132 - RegDbgOut register Reset Function GPIO 1 = Debug mode 00000000 reserved Table 133 - RegDbgMode register ...

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... Personal Area Network TX / CTS Bluetooth Sequencer RX / RTS Bluetooth Sequencer RegDbgDir HCI_DBG_RX Figure 35 – HCI Debug Interface block schematics © Semtech 2006 RTS 1 RegDbgDir RegDbgDir HCI_DBG_TX / HCI_DBG_CTS TX / CTS 0 1 RegDbgDir / 72 Data Sheet SX1441 – Bluetooth® 1.2 SoC UART BT UART BT www.semtech.com ...

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... Data stored in RegDbgOut are output at DBG if RegDbgDir[ The default value after reset is low (0). 3.15.4.2 Debug Mode To enter Debug mode the MSB bit of RegDbgMode register has to be set to 1. © Semtech 2006 0 1 RegDbgDir RegDbgDir PCM_D_OUT / PCM_CLK / PCM_FSYNC ...

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... When in normal operation in applications, DOC_SCK and DOC_SDIO should remain unconnected (N.C) When operated in development / debug mode DOC_SCK and DOC_SDIO, in addition to VDDIO_DIG and VSSIO_DIG, are connected to the SX1441 development tools through the appropriate interface. For more details, please contact Semtech technical support. © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC ...

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... OH V output low voltage OL R internal pull-up resistor pu C input capacitance in Note : Values marked with asterisks are not production tested and guaranteed by design. © Semtech 2006 Conditions See (1) See (2) See (2) pins Table 135 – Absolute maximum ratings Min Typ Max - ...

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... Parked (Slave) Reset (*1) Each slot is used for TX/RX protocol (1 TX for 1 RX) (*2) Each slot is used for TX/RX protocol (5 TX for 5 RX) Table 138 – Typical system current consumption, 3V supply, single 13 MHz crystal © Semtech 2006 VDD_M VREGD VREGA IVDD_radio VDD_DIG SX1441 ...

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... MHz crystal oscillator The on chip regulated voltage units are not used; a stabilized 1.8V supply is used for the complete system. DC 1.8V IVDD Figure 38 – Current measurement diagram, 1.8V supply, single 13 MHz crystal oscillator © Semtech 2006 IVDD_radio VDD_M VREGD IVDD_1441 ...

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... BP 2520 TBD VDDR C23 C8 10pF 0.1 μF PRELIMINARY Bluetooth Headset Reference Design V2.2 Page 1/2 Figure 39 - Headset application schematic, part © Semtech 2006 VDDR VDDR C13 C15 C14 C12 C16 0.1 μF 2.2 μF 10pF 0.1uF 1 nF VDDM REG_BG AREG_VDD C5 2.2 μF ...

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... VREGA C33 C43 VDD_ANA 1 μF 100 nF Q1 VMIC_N C32 C30 220 nF 100 nF C31 220 nF VMIC_P VDDM REG_PD Figure 40 - Headset application schematic, part © Semtech 2006 VDDM J1 SW2 SW1 WAKEUP PB[0] PB[1] PB[2] PB[3] PB[4] PB[5] PB[6] PB[7] SX1441 DBG[0] DBG[1] DBG[2] ...

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... Personal Area Network 6 PACKAGING INFORMATION – 72-PIN LFBGA Figure 41 - Mechanical data for 72 pins LFBGA package (7mmX7mm) Index Pin A1 © Semtech 2006 Figure 42 - Tape & Reel information 80 Data Sheet SX1441 – Bluetooth® 1.2 SoC www.semtech.com ...

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... CoolRISC 816 8-bit Microprocesor Core Hardware and Software Reference Manual, version 4.5, SEMTECH SA. 9 NOTICE, TRADEMARKS Semtech reserves the right to make changes to its products or service without notice. Before using the product, Please make sure that the information being referred to is up-to-date. Bluetooth is a SIG registered trademark, used under license by Semtech ...

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... RegIrqMid RegIrqLow RegIrqEnHig RegIrqEnMid RegIrqEnLow ReqIrqPriority ReqIrqIrq Power Management RegPmgtVrega RegPmgtVregd RegPmgtEol - reserved HCI UART RegHUartFifoCtrl RegHUartFifoBaud © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC Address (Hex) 0x0010 0x0012 0x0013 0x0014 0x0015 0x001B 0x001C 0x001D-0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 ...

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... RegDACSampleH RegDACSampleL RegADCSampleH RegADCSampleL RegDmaRdStartAddrH RegDmaRdStartAddrL RegDmaRdStopAddrH RegDmaRdStopAddrL RegDmaWrStartAddrH RegDmaWrStartAddrL RegDmaWrStopAddrH RegDmaWrStopAddrL RegDmaCtrl RegCodecDataFlow reserved RegADCGain © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC Address (Hex) 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F ...

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... Personal Area Network Subsystem Register Name RegCodecPaMute - reserved - reserved © Semtech 2006 SX1441 – Bluetooth® 1.2 SoC Address (Hex) 0x00F9 0x00FA-0x00FE 0x3FF0–0x3FFF 84 Data Sheet www.semtech.com ...

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... CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. ...