ADF7021-NBCPZ Analog Devices Inc, ADF7021-NBCPZ Datasheet

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... MODULATOR MOD CONTROL CP PFD DIV R OSC CPOUT OSC1 OSC2 Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 High Performance ADF7021-N CE MUXOUT CREG(1:4) LDO(1:4) TEST MUX TxRxCLK CLOCK AND DATA Tx/Rx TxRxDATA RECOVERY CONTROL SWD AGC ...

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... ADF7021-N TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 RF and PLL Specifications........................................................... 4 Transmission Specifications........................................................ 5 Receiver Specifications ................................................................ 6 Digital Specifications ................................................................... 9 General Specifications ............................................................... 10 Timing Characteristics .............................................................. 11 Timing Diagrams........................................................................ 12 Absolute Maximum Ratings.......................................................... 15 ESD Caution................................................................................ 15 Pin Configuration and Function Descriptions........................... 16 Typical Performance Characteristics ........................................... 18 Frequency Synthesizer ...

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... The transmit section contains two voltage controlled oscillators (VCOs) and a low noise fractional-N PLL with an output resolution of <1 ppm. The ADF7021-N has a VCO using an internal LC tank (421 MHz to 458 MHz, 842 MHz to 916 MHz) and a VCO using an external inductor as part of its tank circuit (80 MHz to 650 MHz) ...

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... ADF7021-N SPECIFICATIONS 3.6 V, GND = All measurements are performed with the EVAL-ADF7021-NDBxx using the PN9 data sequence, unless otherwise noted. RF AND PLL SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (RF Divide-by-2 Mode) Phase Frequency Detector (PFD) Frequency PHASE-LOCKED LOOP (PLL) ...

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... PN9 data, 1.2 kHz frequency deviation); 25 kHz channel spacing (9.6 kbps PN9 data, 2.4 kHz frequency deviation) 3.9 kHz 9.9 kHz 4.4 kHz 10.2 kHz 3.9 kHz 9.5 kHz 19.2 kbps PN9 data, 1.2 kHz frequency deviation 13.2 kHz Rev Page 3 25° 25° 25°C A ADF7021-N ...

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... For the definition of frequency deviation, refer to the Register 2—Transmit Modulation Register section. 3 Measured as maximum unmodulated power. 4 Conductive filtered harmonic emissions measured on the EVAL-ADF7021-NDBxx, which includes a T-stage harmonic filter (two inductors and one capacitor). 5 For matching details, refer to the LNA/PA Matching section. RECEIVER SPECIFICATIONS Table 3 ...

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... Rev Page ADF7021-N Test Conditions/Comments f = 2.4 kHz, high sensitivity mode, IF_FILTER_BW = DEV 18.5 kHz, Viterbi detection 2.4 kHz, high sensitivity mode, IF_FILTER_BW = DEV 13.5 kHz, alpha = 0.5, Viterbi detection on f (inner) = 1.2 kHz, high sensitivity mode, DEV IF_FILTER_BW = 13.5 kHz f (inner ...

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... For received signal levels < −100 dBm recommended to average the RSSI readback value over a number of samples to improve the RSSI accuracy at low input powers. 3 Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-NDBxx, which includes a T-stage harmonic filter (two inductors and one capacitor). ...

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... V 0 Rev Page ADF7021-N Test Conditions/Comments CREG (1:4) = 100 nF 32-bit register write time = 50 μs 32-bit register write time = 50 μs, IF filter coarse calibration only Time to synchronized data out, includes AGC settling (three AGC levels)and CDR synchronization; see the AGC Information and Timing section for more details ...

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... Low Current Mode High Sensitivity Mode POWER-DOWN CURRENT CONSUMPTION Low Power Sleep Mode 1 The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-NDBxx evaluation boards. Improved PA efficiency is achieved by using a separate PA matching network. Min Typ Max ...

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... SCLK to SREAD data valid, readback ns SREAD hold time after SCLK, readback ns SCLK to SLE disable time, readback ns TxRxCLK negative edge to SLE ns TxRxDATA to TxRxCLK setup time (Tx mode) ns TxRxCLK to TxRxDATA hold time (Tx mode) μs TxRxCLK negative edge to SLE μs SLE positive edge to positive edge of TxRxCLK Rev Page ADF7021-N ...

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... ADF7021-N TIMING DIAGRAMS Serial Interface SCLK t 1 SDATA DB31 (MSB) SLE SCLK SDATA REG7 DB0 (CONTROL BIT C1) SLE t 3 SREAD t 8 2FSK/3FSK Timing ±1 × DATA RATE/32 TxRxCLK TxRxDATA TxRxCLK TxRxDATA FETCH DB30 DB2 (CONTROL BIT C2) Figure 2. Serial Interface Timing Diagram ...

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... LSB LSB MSB Rx MODE Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode REGISTER 0 WRITE SYMBOL Tx SYMBOL Tx SYMBOL LSB LSB MSB Tx MODE Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode Rev Page ADF7021-N SWITCH FROM SYMBOL Tx SYMBOL Tx SYMBOL MSB LSB MSB Tx MODE SWITCH FROM SYMBOL t BIT ...

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... ADF7021-N UART/SPI Mode UART mode is enabled by setting R0_DB28 to 1. SPI mode is enabled by setting R0_DB28 to 1 and setting R15_DB[17:19] to 0x7. The transmit/receive data clock is available on the CLKOUT pin. CLKOUT (TRANSMIT/RECEIVE DATA CLOCK IN SPI MODE. NOT USED IN UART MODE.) TxRxCLK (TRANSMIT DATA INPUT IN UART/SPI MODE ...

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... This device is a high performance RF integrated circuit with an −40°C to +85°C ESD rating of <2 kV and it is ESD sensitive. Proper precautions −65°C to +125°C should be taken for handling and assembly. 150°C 26°C/W ESD CAUTION 260°C 40 sec Rev Page ADF7021-N ...

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... Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a high impedance CMOS input. 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7021-N to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin. 28 SCLK Serial Clock Input ...

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... Voltage Supply for Digital Block. Place a decoupling capacitor close as possible to this pin. 33 SWD Sync Word Detect. The ADF7021-N asserts this pin when it has found a match for the sync word sequence (see the Register 11—Sync Word Detect Register section). This provides an interrupt for an external microcontroller indicating that valid data is being received. ...

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... ADF7021-N TYPICAL PERFORMANCE CHARACTERISTICS –70 RF FREQ = 900MHz V –80 TEMPERATURE = 25°C VCO_BIAS = 8 VCO_ADJUST = 3 = 0.8mA – –100 –110 I = 2.2mA –120 CP –130 –140 –150 1 10 100 FREQUENCY OFFSET (kHz) Figure 11. Phase Noise Response at 900 MHz PA_BIAS = 11µ PA_BIAS = 9µ PA_BIAS = 5µA –4 PA_BIAS = 7µA – ...

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... MHz Figure 22. 4FSK Sensitivity vs Rev Page ADF7021-N 0 DATA RATE = 1kbps f = 1kHz DEV RF FREQ = 135MHz 12.5kHz 3.0V, +25°C 2.3V, +85°C 3.6V, –40°C –130 –128 –126 –124 –122 –120 –118 –116 –114 –112 –110 –108 ...

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... ADF7021 FREQ = 868MHz 40 WANTED SIGNAL (10dB ABOVE SENSITIVITY 30 POINT) = 2FSK, f DEV 20 DATA RATE = 9.8kbps BLOCKER = 2FSK DEV DATA RATE = 9.8kbps 3.0V DD TEMPERATURE = 25°C –10 –22 –18 –14 –10 –6 – FREQUENCY OFFSET (MHz) Figure 23. Wideband Interference Rejection –20 –40 –60 –80 – ...

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... Figure 30. 3FSK Receiver Eye Diagram Measured Using the Test DAC Output –70 –80 –90 –100 –110 –120 –130 Figure 31. Receive Sensitivity vs. LNA/IF Filter Gain and Mixer Linearity Settings C13 1.7V Rev Page ADF7021-N MODULATION = 2FSK DATA RATE = 9.6kbps f = 4kHz DEV HIGH MIXER 12.5kHz LINEARITY DEMOD = CORRELATOR SENSITIVITY @ 1E-3 BER IP3= –5dBm IP3 = – ...

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... Using a TCXO Reference A single-ended reference (TCXO, VCXO, or OCXO) can also be used with the ADF7021-N. This is recommended for applications having absolute frequency accuracy requirements of <10 ppm, such as applications requiring compliance with ARIB STD-T67 or ETSI EN 300 220. The following are two options for interfacing the ADF7021 external reference oscillator. • ...

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... EVAL-ADF7021-NDBxx should be used for optimum performance. The free design tool ADI SRD Design Studio™ can also be used to design loop filters for the ADF7021-N (see the ADI SRD Design Studio web site for details). N Counter The feedback divider in the ADF7021-N PLL consists of an 8-bit integer counter (R0_DB[19:26]) and a 15-bit, sigma-delta (Σ ...

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... ADF7021-N VOLTAGE CONTROLLED OSCILLATOR (VCO) The ADF7021-N contains two VCO cores. The first VCO, the internal inductor VCO, uses an internal LC tank and supports 842 MHz to 916 MHz and 421 MHz to 458 MHz operating bands. The second VCO, the external inductor VCO, uses an external inductor as part of its LC tank and supports the RF operating band of 80 MHz to 650 MHz ...

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... The occurrence of these spurs is rare because the integer frequencies are around multiples of the reference, which is typically >10 MHz. To avoid having very small or very large values in the fractional register, choose a suitable reference frequency. Rev Page ADF7021-N VCO_ADJUST VCO_BIAS R1_DB[23:24] R1_DB[19:22] 11 ...

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... ADF7021-N TRANSMITTER RF OUTPUT STAGE The power amplifier (PA) of the ADF7021-N is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum frequency of 950 MHz. The PA output current and consequently, the output power, are programmable over a wide range ...

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... P( − D where the convolutional encoder polynomial the unit delay operator. A digital precoder with transfer function 1/P(D) implements an inverse modulo-2 operation of the 1 − D transmitter. Tx DATA 0.25 × DEV Rev Page ADF7021-N C − and the C DEV − f frequency or the f C DEV 0 +1 –1 ...

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... The transmit clock from Pin TxRxCLK is available after writing to Register 3 in the power-up sequence for receive mode. The MSB of the first symbol should be clocked into the ADF7021-N on the first transmit clock pulse from the ADF7021-N after writing to Register 3. Refer to Figure 6 for more timing information ...

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... RF output. The latency without any data filtering is one bit. The addition of data filtering adds a further latency as outlined in Table 12 important that the ADF7021-N be left in transmit mode after the last data bit is sampled by the data clock to account for this latency. The ADF7021-N should stay in transmit mode for a time equal to the number of latency bit periods for the applied modulation scheme ...

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... ADF7021-N RECEIVER SECTION RF FRONT END The ADF7021-N is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerline- induced interference problems. Figure 45 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption to best suit their application ...

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... An additional factor should be introduced to account for losses in the front-end-matching network/antenna. MIXER_LINEARITY Sensitivity (2FSK (R9_DB28) 4.8 kbps −118 1 −114.5 0 −112 1 −105.5 0 −100 1 −92.3 Rev Page ADF7021-N Number of AGC = Settling Time [sec] AGC Update Mode Correction) × 0.5 Filter Gain Gain Mode (FG2, FG1) Correction ...

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... DEMODULATION, DETECTION, AND CDR System Overview An overview of the demodulation, detection, and clock and data recovery (CDR) of the received signal on the ADF7021-N is shown in Figure 47. The quadrature outputs of the IF filter are first limited and then fed to either the correlator FSK demodulator or to the linear FSK demodulator ...

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... However, this tolerance is reduced during recovery of the remainder of the packet where symbol transi- tions may not be guaranteed to occur at regular intervals. To maximize the data rate tolerance of the CDR, some form of encoding and/or data scrambling is recommended that guarantees a number of transitions at regular intervals. Rev Page ADF7021-N ...

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... ADF7021-N For example, using 2FSK with Manchester-encoded data achieves a data rate tolerance of ±2.0%. The CDR PLL is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchro- nization within 5-symbol transitions of preamble. In 4FSK modulation, the tolerance using the +3, −3, +3, −3 preamble is ± ...

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... Recommended Setting 1 ⎛ Transmit F requency Deviation × ⎜ 62 × ⎝ 3 100 10 where K is the value calculated for correlator discriminator bandwidth. 15 Rev Page ADF7021-N × ⎛ ⎞ 4FSK Outer Tx Deviation K × ⎜ ⎜ ⎟ ⎟ × 3 ⎝ ⎠ 100 10 Purpose Phase correction is on × ...

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... When the receiver uses the internal AFC, the minimum recommended number of preamble bits is 64. The remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7021-N can accommodate coding schemes with a run length of greater than eight bits without any performance degradation. Refer to Application Note AN-915 for more information ...

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... ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7021-N. In receive mode, this preprogrammed word is compared to the received bit stream. When a valid match is identified, the external SWD pin is asserted by the ADF7021-N on the next Rx clock pulse. ⎛ × ⎞ ...

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... It is recommended to perform a coarse calibration on every receive mode power-up. This calibration typically takes 200 μs. The FILTER_CAL_COMPLETE signal from MUXOUT can be used to monitor the filter calibration duration or to signal the end of calibration. The ADF7021-N should not be accessed during calibration. Rev Page XTAL × ...

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... IF Filter Variation with Temperature When calibrated, the filter center frequency can vary with changes in temperature. If the ADF7021-N is used in an application where it remains in receive mode for a considerable length of time, the user must consider this variation of filter center frequency with temperature. This variation is typically 1 kHz per 20° ...

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... Table 15. _PA. OPT IMAGE REJECTION CALIBRATION The image channel in the ADF7021-N is 200 kHz below the PA_OUT desired signal. The polyphase filter rejects this image with an PA asymmetric frequency response. The image rejection performance ...

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... IR_GAIN_ADJUST_I/Q bit (R5_DB30), whereas the IR_GAIN_ADJUST_UP/DN bit (R5_DB31) sets whether the gain adjustment defines a gain or an attenuation adjust. The calibration results are valid over changes in the ADF7021-N supply voltage. However, there is some variation with temperature. A typical plot of variation in image rejection over temperature after initial calibrations at − ...

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... PROGRAMMING AFTER INITIAL POWER-UP Table 23 lists the minimum number of writes needed to set up the ADF7021-N in either mode after CE is brought high. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from vice versa, the user needs to toggle the Tx/Rx bit and write only to Register 0 to alter the LO by 100 kHz ...

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... WRITE TO REGISTER 2 (TURNS OFF PA) WAIT FOR PA TO RAMP DOWN OPTIONAL. ONLY NECESSARY IF PA RAMP DOWN IS REQUIRED. Figure 55. Power-Up Sequence for Transmit Mode XTAL REFERENCE POWER-DOWN CE LOW WAIT 10µs + 1ms (REGULATOR POWER-UP + TYPICAL XTAL SETTLING) Tx MODE (REFER TO TABLE 12) CE LOW POWER-DOWN Rev Page ADF7021-N CE HIGH ...

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... ADF7021-N REFERENCE CE HIGH WAIT 10µs (REGULATOR POWER-UP) OPTIONAL. TCXO POWER-DOWN CE LOW WRITE TO REGISTER 1 (TURNS ON VCO) WAIT 0.7ms (TYPICAL VCO SETTLING) WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS) WRITE TO REGISTER 6 (SETS UP IF FILTER CALIBRATION) WRITE TO REGISTER 5 (STARTS IF FILTER CALIBRATION) WAIT 0.2ms (COARSE CAL) OR WAIT 8.2ms ...

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... APPLICATIONS CIRCUIT The ADF7021-N requires very few external components for operation. Figure 57 shows the recommended application circuit. Note that the power supply decoupling and regulator capacitors are omitted for clarity. MATCHING T-STAGE LC ANTENNA FILTER CONNECTION RESISTOR *PIN 44 AND PIN 46 CAN BE LEFT FLOATING IF EXTERNAL INDUCTOR VCO IS NOT USED. ...

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... ADF7021-N SERIAL INTERFACE The serial interface allows the user to program the 16-/32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, 32-bit shift register, and 16 latches. Signals should be CMOS compatible. The serial interface is powered by the regulator, and, therefore, is inactive when CE is low. ...

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... BCD format. The product code (PC) is coded with three quartets extending from Bit RV5 to Bit RV16. The revision code (RC) is coded with one quartet extending from Bit RV1 to Bit RV4. The product code for the ADF7021-N should read back 0x211. The current revision code should read 0x1. ...

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... Figure 4 and Figure 5 for the relevant timing diagrams. In 4FSK transmit mode, the MSB of the transmit symbol is clocked into the ADF7021-N on the first rising edge of the data clock from the TxRxCLK pin. In 4FSK receive mode, the MSB of the first payload symbol is clocked out on the first negative edge of the data clock after the SWD and should be clocked into the microcontroller on the following rising edge ...

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... Figure 63. Register 0—N Register Map • ⎞ ⎟ ⎠ • ⎞ Fractional ⎟ 15 ⎠ 2 Rev Page ADF7021-N ADDRESS BITS FRACTIONAL_N M15 M14 M13 ... DIVIDE RATIO ... ... ... ... . . . . . . . ... . . . ...

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... ADF7021-N REGISTER 1—VCO/OSCILLATOR REGISTER VCO CENTER VA2 VA1 FREQ ADJUST 0 0 NOMINAL 0 1 VCO ADJUST VCO ADJUST VCO ADJUST UP 3 VB4 VB3 VB2 VB1 VCL1 VCO_INDUCTOR 0 INTERNAL L VCO 1 EXTERNAL L VCO • The R_COUNTER and XTAL_DOUBLER relationship is as follows: If XTAL_DOUBLER = 0, PFD If XT ...

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... R-COSINE_ALPHA sets the roll-off factor (alpha) of the raised cosine data filter to either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7. ADF7021-N ADDRESS BITS ...

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... ADF7021-N REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER AGC_CLK_DIVIDE SEQ_CLK_DIVIDE GD4 GD3 GD2 GD1 GD6 GD5 ... ... ... ... ... ... • Baseband offset clock frequency (BBOS CLK) must be greater than 1 MHz and less than 2 MHz, where XTAL = BBOS CLK BBOS _ CLK _ DIVIDE • Set the demodulator clock (DEMOD CLK) such that 2 MHz ≤ ...

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... RESERVED is rounded to the nearest of the following integers: 4FSK is the transmit frequency deviation in Hz. For 4FSK, DEV is the frequency deviation used for the ±1 symbols DEV × × π CUTOFF POST_DEMOD _BW DEMOD CLK cutoff frequency ( the post demod- CUTOFF ADF7021-N BITS ...

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... ADF7021-N REGISTER 5—IF FILTER SETUP REGISTER IR_GAIN_ ADJUST_MAG PM3 PD1 IR_PHASE_ADJUST_DIRECTION 0 ADJUST ADJUST Q CH GM5 GM4 GM3 GM2 GM1 GQ1 IR_GAIN_ADJUST_I/Q 0 ADJUST ADJUST Q CH GA1 IR_GAIN_ADJUST_UP/DN 0 GAIN 1 ATTENUATE • A coarse IF filter calibration is performed when the IF_CAL_COARSE bit (R5_DB4) is set. If the IF_FINE_ ...

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... DRIVE_LEVEL bits (R6_DB[28:29]) set the drive strength of the source, whereas the IR_CAL_SOURCE_÷2 bit (R6_DB30) allows the frequency of the internal signal source to be divided by 2. Upper Tone Frequency 116.3 kHz 116.3 kHz 119 kHz Rev Page ADF7021-N IF_CAL_LOWER_TONE_DIVIDE FC1 IF_FINE_CAL 0 DISABLED 1 ENABLED IF_CAL_LOWER_ LT3 ...

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... ADF7021-N REGISTER 7—READBACK SETUP REGISTER RB3 READBACK_SELECT 0 DISABLED 1 ENABLED • Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, temperature sensor, or voltage at the external pin is not valid in Rx mode. • To read back the battery voltage, the temperature sensor, or ...

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... C4 (1) C3 (0) C2 (0) C1 (0) PD1 SYNTH_ENABLE 0 SYNTH OFF 1 SYNTH ON PD3 LNA/MIXER_ENABLE 0 LNA/MIXER OFF 1 LNA/MIXER ON PD4 FILTER_ENABLE 0 FILTER OFF 1 FILTER ON For a combined LNA/PA matching network, R8_DB11 should always be set to 0, which enables the internal Tx/Rx switch. This is the power-up default condition. ADF7021-N ...

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... ADF7021-N REGISTER 9—AGC REGISTER ML1 MIXER_LINEARITY 0 DEFAULT 1 HIGH LI2 LI1 LNA_BIAS 0 0 800µA (DEFAULT) LG1 LNA_MODE 0 DEFAULT 1 REDUCED GAIN FI1 FILTER_CURRENT 0 LOW 1 HIGH FG2 FG1 FILTER_GAIN INVALID • necessary to program this register only if AGC settings, other than the defaults, are required. ...

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... Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the AFC. Rev Page ADF7021-N ADDRESS BITS AE1 AFC_EN 0 ...

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... ADF7021-N REGISTER 11—SYNC WORD DETECT REGISTER REGISTER 12—SWD/THRESHOLD SETUP REGISTER SWD_MODE 0 SWD PIN LOW 1 SWD PIN HIGH AFTER NEXT SYNCWORD 2 SWD PIN HIGH AFTER NEXT SYNCWORD FOR DATA PACKET LENGTH NUMBER OF BYTES 3 INTERRUPT PIN HIGH Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation and locking the AFC and AGC loops when using linear or correlator demodulation ...

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... OFF PHASE_ 2 PC1 1 1 CORRECTION DISABLED . . . 1 ENABLED 1 1 127 ST7 VITERBI_PATH _ 0 MEMORY VM2 VM1 BITS BITS . BITS . BITS 1 Figure 76. Register 13—3FSK/4FSK Demod Register Map Rev Page 3FSK/4FSK_ CONTROL SLICER_THRESHOLD BITS SLICER ST3 ST2 ST1 ... THRESHOLD 0 0 ... 0 OFF ... ... 2 ... ... . . . . ... . . . . ... 127 ADF7021-N ...

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... ADF7021-N REGISTER 14—TEST DAC REGISTER TEST_DAC_GAIN ED_LEAK_FACTOR PULSE_EXTENSION LEAKAGE = 0 0 2^– 2^– 2^– 2^–11 4 2^–12 5 2^–13 6 2^–14 7 2^–15 ED_PEAK_RESPONSE 0 FULL RESPONSE TO PEAK 1 0.5 RESPONSE TO PEAK 2 0.25 RESPONSE TO PEAK 3 0.125 RESPONSE TO PEAK The demodulator tuning parameters, PULSE_EXTENSION, ED_LEAK_FACTOR, and ED_PEAK_RESPONSE, can be enabled only by setting R15_DB[4:7] to 0x9 ...

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... BB OFFSET CLK 5 SIGMA DELTA CLK 6 ADC CLK 7 TxRxCLK Figure 78. Register 15—Test Mode Register Map • The CDR block can be bypassed by setting Rx_TEST_ MODES depending on the demodulator used. Rev Page ADF7021-N Tx_TEST_ Rx_TEST_ ADDRESS MODES MODES BITS Rx_TEST_MODES 0 NORMAL 1 SCLK, SDATA -> ...

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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADF7021-NBCPZ −40°C to +85°C 1 ADF7021-NBCPZ-RL −40°C to +85°C 1 ADF7021-NBCPZ-RL7 −40°C to +85°C ADF7021-NDF −40°C to +85°C 1 EVAL-ADF70XXMBZ2 1 EVAL-ADF7021-NDBIZ 1 EVAL-ADF7021-NDBEZ 1 EVAL-ADF7021-NDBZ2 1 EVAL-ADF7021-NDBZ5 RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...