SI4201-BM Silicon Laboratories Inc, SI4201-BM Datasheet
SI4201-BM
Specifications of SI4201-BM
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SI4201-BM Summary of contents
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... RFOD IOP 2 23 VDD CKN 3 22 RFIGN CKP 4 GND 21 RFIGP PAD TXIP 5 20 RFIDN TXIN 6 19 RFIDP TXQP 7 18 RFIPN TXQN 8 17 RFIPP Si4201- GND 1 15 SDO RXQP 2 14 PDN GND RXQN 3 13 XEN PAD RXIP 4 12 ION RXIN 5 11 IOP ...
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Aero+ 2 Rev. 1.2 ...
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... Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 XDRV Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 XOUT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Descriptions: Si4200- .38 Pin Descriptions: Si4200DB- Pin Descriptions: Si4201- .40 Pin Descriptions: Si4134T- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package Outline: Si4200-BM and Si4200DB- Package Outline: Si4201- .44 Package Outline: Si4134T- Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Rev. 1.2 Aero+ Page 3 ...
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Aero+ Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at 2.85 V and an ...
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... Table 3. DC Characteristics (V = 2 – ° Parameter Si4200 Supply Current 1 Si4201 Supply Current 2 Si4134T Supply Current Total Chipset Supply Current 3 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Current 3 Low Level Input Current 4 High Level Output Voltage ...
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Aero+ Table 4. AC Characteristics (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time PDN Rise Time PDN Fall ...
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D17 D16 SDI 50% 20 HOLD 80% SCLK 50% 20 EN1 CLK 80% SEN 50% 20% Figure 3. Serial Interface Write Timing Diagram 80% A0 SDI 50% 20% 80% SDO ...
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Aero+ Table 5. Receiver Characteristics (V = 2 – ° Parameter 1 GSM Input Frequency 1 DCS or PCS Input Frequency 2,3 Noise Figure ° 2,3 Noise Figure ...
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... Voltage gain is defined as the differential rms voltage at the LNA output divided by the rms voltage at the balun output. 9. Output pins RXIP, RXIN, RXQP, RXQN. 10. The baseband signal path is entirely digital. Gain, phase, and offset errors at the baseband outputs are because of the Si4201 D/A converters. Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description. ...
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Aero+ −20 −40 −60 −80 −100 −120 Figure 5. Receive Path Magnitude Response (CSEL = −2 −4 −6 −8 −10 −12 −14 −16 Figure 6. Receive Path Passband Magnitude Response (CSEL = ...
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Receive Path Magnitude Response (CSEL = 1) 0 −20 −40 −60 − 100 150 Figure 8. Receive Path Magnitude Response (CSEL = 1) Receive Path Passband Magnitude Response (CSEL = −2 −4 −6 −8 −10 ...
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Aero+ Table 6. Transmitter Characteristics (V = 2 – ° Parameter 1 RFOG Output Frequency 2 RFOD Output Frequency 3,4 I/Q Differential Input Swing 3 I/Q Input Common-Mode 3,4 I/Q Differential ...
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Table 6. Transmitter Characteristics (Continued 2 – ° Parameter 1,2 RF Output Harmonic Suppression 5,8 Powerup Settling Time Notes: 1. Measured at RFOG pin. 2. Measured at RFOD pin. ...
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Aero+ Table 7. Frequency Synthesizer Characteristics (V = 2 – ° Parameter 1 RF1 VCO Frequency 1 RF2 VCO Frequency 1 IF VCO Frequency RF1 PLL Phase Detector Update Frequency IF ...
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Table 7. Frequency Synthesizer Characteristics (Continued 2 – ° Parameter 3 RF1 PLL Spurious 3 RF2 PLL Spurious 3 IF PLL Spurious Notes: 1. For the GSM input, the ...
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... Typical Triple-Band Application Schematic PDN SEN SCLK SDO VDD C10 1 GND SDO 2 RXQP RXQP PDN U2 3 RXQN RXQN XOE SI4201 4 RXIP RXIP ION 5 RXIN RXIN IOP VDD C9 TXIP TXIN TXQP TXQN C7 XTAL_EN XAFC Notes: 1. Connect GND pad on bottom of U1–U3 to GND. ...
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... Murata LQW18AN series (0603 size) Murata LQW15A series (0402 size) Murata LQW18AN series (0603 size) Murata LQW15A series (0402 size) Multi-layer (0402 or 0603 size) PCB Trace Silicon Laboratories Si4200-BM Silicon Laboratories Si4201-BM Silicon Laboratories Si4134T-BM = 8.0 pF KDS BR13000AA0E L KSS CX96FFFBQAJ13 EPCOS B39881-B7719-C610 (6-pin, 2.0x2.5 mm) EPCOS B39881-B9001-C710 (5-pin, 1 ...
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... The Aero+ transceiver is the industry’s most integrated RF front end for multi-band GSM/GPRS digital cellular handsets and wireless data modems. The chipset consists of the Si4200 GSM transceiver, Si4201 universal baseband interface, and Si4134T dual RF synthesizer with an integrated digitally-controlled crystal oscillator (DCXO). The highly integrated solution ...
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... IF signal is digitized with high resolution A/D converters (ADCs). the low-IF The Si4201 downconverts the ADC output to baseband with a digital 100 kHz quadrature LO signal. Digital decimation and IIR filters perform channel selection to remove blocking and reference interference signals. The response of the IIR filter is programmable to a high selectivity setting (CSEL = low selectivity setting (CSEL = 1) ...
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Aero+ Transmit Section REG GSM PA ÷ DCS/PCS TXBAND[1:0] The transmit (TX) section consists of an I/Q baseband upconverter, an offset phase-locked loop (OPLL), and two output buffers that can drive external power amplifiers (PA): one for the ...
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Frequency Synthesizer XAFC ÷1,2 XTALEN DCXO XTAL1 DIV2 XTAL2 CDAC[5:0] XDRV XDRVEN Power PDIB PDN Control PDRB SDI SCLK Serial SDOSEL[3:0] I/O SEN SDO Figure 14. Si4134T Frequency Synthesizer Block Diagram The Si4134T dual frequency synthesizer is a monolithic CMOS ...
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Aero+ VCO Inductor Design C VAR PLL Determining L EXT The center frequencies for the RF2, and IF VCOs in the Si4134T are set using an external inductance (L is very important that L be properly designed to EXT ensure ...
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... MHz reference clock for the system. The Si4134T generates a single-ended MHz output (XDRV) to drive the Si4201, and the Si4201 then buffers MHz reference clock (XOUT sent to other system components such as the baseband. The complete circuit is shown in the "Typical Triple-Band Application Schematic" ...
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... XIN pin on the Si4201. To Address Field achieve complete powerdown during sleep, the XEN pin must be set low, the XBUF bit in Register 12 must be set to 0, and the XPD1 bit in Register 11 must be set to 1. During normal operation, these bits should set to their default values ...
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... Name D17 D16 D15 D14 D13 D12 D11 D10 D9 Si4200 00h Revision/Read 01h Reset 02h Mode 03h Config 04h Transmit 05h Receive Si4201 10h Revision/Read 11h Config 12h DAC Config 19h Reserved 20h RX Master #1 RXBAND[1:0] 21h RX Master #2 0 DPDS[2:0] 22h RX Master # ...
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... Name Bit Name 17:8 Reserved 7:0 REV0[7:0] Note: Registers on the Si4200 can be read by writing this register with the address of the register to be read. Register 01h. Reset (Si4200/Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:1 Reserved ...
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... Register 02h. Mode Control (Si4200/Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:3 Reserved 2 AUTO 1:0 MODE[1:0] Note: Calibration must be performed each time the power supply is applied. To initiate the calibration mode, set MODE[1:0] = 10, and pulse the PDN pin high for at least 150 µs. ...
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Aero+ Register 03h. Configuration (Si4200) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name DIAG[1:0] Bit Name 17:14 Reserved 13:12 DIAG[1:0] 11 SWAP 10:8 Reserved 7:6 TXBAND[1:0] 5:4 RXBAND[1:0] 3:2 Reserved 1 Reserved 0 Reserved ...
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Register 04h. Transmit Control (Si4200) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:11 Reserved 10 Reserved 9:8 BBG[1:0] 7:4 FIF[3:0] 3:0 Reserved BBG[1:0] ...
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... Aero+ Register 05h. Receive Gain (Si4200/Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:14 Reserved 13:8 DGAIN[5:0] 7 Reserved 6:4 AGAIN[2:0] 3:2 LNAC[1:0] 1:0 LNAG[1: DGAIN[5:0] 0 Function Program to zero. Digital PGA Gain Control. 00h = 0 dB (default). 01h = 1 dB. ...
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... Name Bit Name 17:8 Reserved 7:0 REV1[7:0] Note: Registers on the Si4201 can be read by writing this register with the address of the register to be read. Register 11h. Configuration (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:14 Reserved ...
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... Reference Buffer Power Control Reference buffer disabled Reference buffer automatically enabled (default). Note: This bit should be set to 1 during normal operation. To achieve the lowest Si4201 power down current (I PDN1 bit in Register 12h must also be set appropriately. Program to zero. ZERODEL Band Select. ...
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... Register 19h. Reserved (Si4201) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:0 Reserved Register 20h. RX Master #1 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name RXBAND[1:0] Notes: 1. See registers 03h and 33h for bit definitions. ...
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Aero+ Register 24h. TX Master #2 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name FIF[3:0] Note: See registers 04h and 35h for bit definitions. Register 28h. CDAC (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 Name ...
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Register 31h. Main Configuration (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name SDOSEL[3:0] Bit Name 17:15 Reserved 14:11 SDOSEL[3:0] 10:5 Reserved 4 RFUP 3 DIV2 2:0 Reserved ...
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Aero+ Register 32h. Powerdown (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Register 33h. RF1 N Divider (Si4134T) Bit D17 D16 D15 D14 ...
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Register 35h Divider (Si4134T) Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name 17:16 Reserved Program to zero. 15:0 N [15:0] N Divider for IF Synthesizer. IF Used for transmit mode. D8 ...
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... RFIPP Top View Description Data output to Si4201 (differential). Clock input from Si4201 (differential). Transmit I input (differential). Transmit Q input (differential). IFLO Input from Si4133T (differential). Ground. Connect to ground plane on PCB. RFLO Input from Si4133T (differential). Supply voltage. Diagnostic output. Can be used as digital outputs to control antenna switch functions. ...
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... RFIPP Top View Description Data output to Si4201 (differential). Clock input from Si4201 (differential). Transmit I input (differential). Transmit Q input (differential). IFLO Input from Si4134T (differential). RFLO Input from Si4134T (differential). Supply voltage. Diagnostic output. Can be used as digital outputs to control antenna switch functions. ...
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... Aero+ Pin Descriptions: Si4201-BM Pin Number(s) Name 2, 3 RXQP, RXQN 4, 5 RXIP, RXIN XIN 9, 10 CKP, CKN 11, 12 IOP, ION 13 XEN 14 PDN 15 SDO 16 SEN 17 SCLK 18 SDI 19 XOUT 1, 8, GND GND pad GND 1 15 SDO RXQP 2 14 PDN GND RXQN 3 13 XEN ...
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... Top View Description Tuning inductor connection for IF VCO. Power down input (active low). XDRV enable. Reference clock output to Si4201. Supply voltage. No connect. Crystal input. Crystal output. Crystal enable. Baseband AFC signal input. Serial enable input (active low). Serial clock input. Serial data input. ...
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... GSM 850 or E-GSM 900, DCS 1800, PCS 1900 Si4200DB-BM Dual-Band Aero Transceiver GSM 850/PCS 1900 or E-GSM 900/DCS 1800 Si4200DB-GM Dual-Band Aero Transceiver GSM 850/PCS 1900 or E-GSM 900/DCS 1800 Si4201-BM Universal Baseband Interface Si4201-GM Universal Baseband Interface Si4134T-BM Dual RF Synthesizer with DCXO ...
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Package Outline: Si4200-BM and Si4200DB-BM Figure 18 illustrates the package details for the Si4200-BM and Si4200DB-BM. Table 12 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View ...
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... Aero+ Package Outline: Si4201-BM Figure 19 illustrates the package details for the Si4201-BM. Table 13 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View Figure 19. 20-Pin Micro Leadframe Package (MLP) Symbol Millimeters Min Nom A — 0.85 A1 0.00 0.01 A2 — ...
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Package Outline: Si4134T-BM Figure 18 illustrates the package details for the Si4134T-BM. Table 12 lists the values for the dimensions shown in the illustration PIN1 ID 0.50 DIA Top View Figure 20. 32-Pin Micro ...
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... Outline: Si4200-BM and Si4200DB-BM" on page 43 (documentation change only, no change to part) Updated D2,E2 dimensions. Updated device weight. Added notes 5 and 6. "Package Outline: Si4201-BM" on page 44 (documentation change only, no change to part) Updated L dimension. Updated device weight. Added notes 5 and 6. "Package Outline: Si4134T-BM" on page 45 (documentation change only, no change to part) Updated L dimension ...
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Notes: Rev. 1.2 Aero+ 47 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and Aero are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder 48 Rev ...