SI4430-B1-FMR Silicon Laboratories Inc, SI4430-B1-FMR Datasheet - Page 42

• Manufacturer Part Number: SI4430-B1-FMR
• Description: IC TXRX 900-960MHZ -8-13DB 20QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4430-B1-FMR

• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 900MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Si4430/31/32-B1
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the
incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcontroller via the
nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be enabled by
setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and “Register 06h. Interrupt Enable 2.” If the
interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read
correctly in the Interrupt Status registers.
6.2. Packet Configuration
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Register 30h.
Data Access Control" through “Register 4Bh. Received Packet Length” control the configuration, status, and
decoded RX packet data for Packet Handling. The usual fields for network communication (such as preamble,
synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data
payload. The fields needed for packet generation normally change infrequently and can therefore be stored in
registers. Automatically adding these fields to the data payload greatly reduces the amount of communication
between the microcontroller and the Si4430/31/32 and reduces the required computational power of the
microcontroller.
The general packet structure is shown in Figure 18. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable
lengths to accommodate different applications. The most common CRC polynominals are available for selection.
An overview of the packet handler configuration registers is shown in Table 13.
42
Add R/W
Add R/W
7C
7D
08
7E
R/W
R/W
R/W
R/W
1-255 Bytes
Preamble
Description
Description
Operating &
Function/
Function/
Control 2
Control 1
Control 2
Function
TX FIFO
TX FIFO
RX FIFO
Control
1-4 Bytes
Reserved Reserved txafthr[5]
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0]
Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0]
antdiv[2]
D7
D7
antdiv[1]
D6
D6
Figure 18. Packet Structure
antdiv[0]
D5
D5
Rev 1.1
txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0]
rxmpk
D4
D4
Data
autotx
D3
D3
enldm
D2
D2
ffclrrx
D1
D1
0 or 2
Bytes
ffclrtx
CRC
D0
D0
POR
Def.
POR
37h
Def.
00h
37h
04h