PIC18F87J72-I/PT Microchip Technology, PIC18F87J72-I/PT Datasheet
PIC18F87J72-I/PT
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PIC18F87J72-I/PT Summary of contents
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... Microcontrollers with Dual Channel AFE, LCD Driver and nanoWatt Technology 2010 Microchip Technology Inc. PIC18F87J72 Family Data Sheet 80-Pin, High-Performance Preliminary DS39979A ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... MHz • Secondary Oscillator using Timer1 at 32 kHz • Fail-Safe Clock Monitor (FSCM): - Allows for safe shutdown if peripheral clock fails 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Low-Power Features: • Power-Managed modes: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off • ...
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... PIC18F87J72 FAMILY Flash SRAM Program Data Device Memory Memory (Pixels) (bytes) (bytes) PIC18F86J72 64K 3,923 PIC18F87J72 128K 3,923 Pin Diagram (1) 80-Pin TQFP 80 79 CH0+ 1 CH0- 2 RE1/LCDBIAS2 3 RE0/LCDBIAS1 4 RG0/LCDBIAS0 5 RG1/TX2/CK2 6 RG2/RX2/DT2/V 1 LCAP 7 RG3/V 2 LCAP 8 MCLR 9 RG4/SEG26/RTCC DDCORE CAP 12 RF7/AN5/SS/SEG25 13 RF6/AN11/SEG24/C1INA 14 RF5/AN10/CV /SEG23/C1INB ...
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... Rogowski coils. 2: Power metering, with the measurement of active and reactive power, is done with the power metering firmware application available through Microchip Technology. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 10 MHz 32 kHz MAIN OSC H/W RTCC ...
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... PIC18F87J72 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 21 3.0 Oscillator Configurations ............................................................................................................................................................ 25 4.0 Power-Managed Modes ............................................................................................................................................................. 35 5.0 Reset .......................................................................................................................................................................................... 43 6.0 Memory Organization ................................................................................................................................................................. 55 7.0 Flash Program Memory .............................................................................................................................................................. 77 8 Hardware Multiplier............................................................................................................................................................ 87 9.0 Interrupts .................................................................................................................................................................................... 89 10.0 I/O Ports ................................................................................................................................................................................... 105 11.0 Timer0 Module ......................................................................................................................................................................... 123 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Preliminary DS39979A-page 7 ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 8 Preliminary 2010 Microchip Technology Inc. ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F87J72 family offer six different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • ...
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... The AFE is controlled, and its data read, through a dedicated, high-speed (20 MHz) SPI interface. • 12-Bit A/D Converter: In addition to the AFE, PIC18F87J72 family devices also include a stan- dard SAR A/D Converter with 12 independent analog inputs. The module incorporates program- mable acquisition time, allowing for a channel to ...
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... Details on Individual Family Members Devices in the PIC18F87J72 family are available in 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1. TABLE 1-1: DEVICE FEATURES FOR THE PIC18F8XJ72 (80-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) ...
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... PIC18F87J72 FAMILY FIGURE 1-1: PIC18F8XJ72 (80-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATU 21 20 PCU Program Counter 31-Level Stack Address Latch Program Memory (96 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode and Control Timing Power-up OSC2/CLKO Generation ...
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... P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device ...
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... PIC18F87J72 FAMILY TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/SEG30 57 RB0 INT0 SEG30 RB1/INT1/SEG8 56 RB1 INT1 SEG8 RB2/INT2/SEG9/ 55 CTED1 RB2 INT2 CTED1 SEG9 RB3/INT3/SEG10/ 54 CTED2 RB3 INT3 SEG10 CTED2 RB4/KBI0/SEG11 53 RB4 KBI0 SEG11 RB5/KBI1/SEG29 52 RB5 KBI1 ...
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... Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. ...
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... PIC18F87J72 FAMILY TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/SEG0/CTPLS 73 RD0 SEG0 CTPLS RD1/SEG1 68 RD1 SEG1 RD2/SEG2 67 RD2 SEG2 RD3/SEG3 66 RD3 SEG3 RD4/SEG4 65 RD4 SEG4 RD5/SEG5 63 RD5 SEG5 RD6/SEG6 62 RD6 SEG6 RD7/SEG7 61 RD7 SEG7 Legend: TTL = TTL compatible input ...
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... Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O. ...
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... PIC18F87J72 FAMILY TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF1/AN6/C2OUT/ 21 SEG19 RF1 AN6 C2OUT SEG19 RF2/AN7/C1OUT/ 18 SEG20 RF2 AN7 C1OUT SEG20 RF3/AN8/SEG21/ 17 C2INB RF3 AN8 SEG21 C2INB RF4/AN9/SEG22/ 16 C2INA RF4 AN9 SEG22 C2INA RF5/AN10/ REF SEG23/C1INB ...
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... Input P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O. ...
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... PIC18F87J72 FAMILY TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RESET SAV 74 DD CH0+ 1 CH0- 2 CH1- 19 CH1+ 20 SAV 26 SS REFIN+/OUT 28 REFIN+ REFOUT REFIN CLKIA 41 CSA 58 SCKA 59 SDOA 60 SDIA 64 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F87J72 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V ...
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... PIC18F87J72 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes recommended to keep the trace length between the ...
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... PIC18F87J72 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types The PIC18F87J72 family of devices can be operated in eight different oscillator modes: 1. ECPLL OSC1/OSC2 as primary; ECPLL oscillator with PLL enabled, CLKO on RA6 2. EC OSC1/OSC2 as primary; external clock with F /4 output OSC 3. HSPLL OSC1/OSC2 as primary; high-speed crystal/resonator with software PLL control 4 ...
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... PIC18F87J72 FAMILY 3.2 Control Registers The OSCCON register (Register 3-1) controls the main aspects of the device clock’s operation. It selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. ...
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... Monitor. The internal oscillator block is discussed in more detail in Section 3.5 “Internal Oscillator Block”. The PIC18F87J72 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. When an alternate clock source is enabled, various power-managed operating modes are available ...
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... SCS<1:0> bits at any given time. 3.3.2 OSCILLATOR TRANSITIONS PIC18F87J72 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 3-2 for additional information. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq. ...
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... PIC18F87J72 FAMILY 3.4.2 EXTERNAL CLOCK INPUT (EC MODES) The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided available on the OSC2 pin ...
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... Internal Oscillator Block The PIC18F87J72 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcon- troller’s clock source. This may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. ...
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... PIC18F87J72 FAMILY 3.5.3 INTERNAL OSCILLATOR OUTPUT FREQUENCY AND TUNING The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8 MHz. It can be adjusted in the user’s application by writing to TUN<5:0> (OSCTUNE<5:0>) in the register (Register 3-2). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency ...
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... MSSP slave, INTx pins and others). Peripherals that may add significant current Section 29.2 “DC Characteristics: Power-Down and Supply Current PIC18F87J72 Family (Industrial)”. 3.7 Power-up Delays and Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applica- tions ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 34 Preliminary 2010 Microchip Technology Inc. ...
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... POWER-MANAGED MODES The PIC18F87J72 family devices provide the ability to manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F87J72 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its ...
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... OST OSC PLL 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run ...
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... PIC18F87J72 FAMILY 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times ...
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... These intervals are not shown to scale. OST OSC PLL 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... PIC18F87J72 FAMILY 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 42 Preliminary 2010 Microchip Technology Inc. ...
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... RESET The PIC18F87J72 family of devices differentiates between various kinds of Reset: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during power-managed modes • Watchdog Timer (WDT) Reset (during execution) • Brown-out Reset (BOR) • Configuration Mismatch (CM) • ...
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... PIC18F87J72 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 IPEN — CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16XXXX Compatibility mode) bit 6 Unimplemented: Read as ‘ ...
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... To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 5.4 Brown-out Reset (BOR) The PIC18F87J72 family of devices incorporates a simple BOR function when the internal regulator is enabled (ENVREG pin is tied The voltage reg- DD ...
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... Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87J72 fam- ily devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc. PIC18F87J72 FAMILY T PWRT , V RISE > 3. PWRT Preliminary ): CASE PWRT ...
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... PIC18F87J72 FAMILY 5.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F87J72 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices FSR1H PIC18F8XJ72 FSR1L PIC18F8XJ72 BSR PIC18F8XJ72 INDF2 PIC18F8XJ72 POSTINC2 PIC18F8XJ72 POSTDEC2 PIC18F8XJ72 PREINC2 PIC18F8XJ72 PLUSW2 PIC18F8XJ72 FSR2H PIC18F8XJ72 FSR2L PIC18F8XJ72 STATUS PIC18F8XJ72 TMR0H PIC18F8XJ72 TMR0L PIC18F8XJ72 T0CON PIC18F8XJ72 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F87J72 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices IPR3 PIC18F8XJ72 PIR3 PIC18F8XJ72 PIE3 PIC18F8XJ72 IPR2 PIC18F8XJ72 PIR2 PIC18F8XJ72 PIE2 PIC18F8XJ72 IPR1 PIC18F8XJ72 PIR1 PIC18F8XJ72 PIE1 PIC18F8XJ72 OSCTUNE PIC18F8XJ72 TRISG PIC18F8XJ72 TRISF PIC18F8XJ72 TRISE PIC18F8XJ72 TRISD PIC18F8XJ72 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F87J72 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices SPBRG2 PIC18F8XJ72 RCREG2 PIC18F8XJ72 TXREG2 PIC18F8XJ72 TXSTA2 PIC18F8XJ72 RCSTA2 PIC18F8XJ72 RTCCFG PIC18F8XJ72 RTCCAL PIC18F8XJ72 RTCVALH PIC18F8XJ72 RTCVALL PIC18F8XJ72 ALRMCFG PIC18F8XJ72 ALRMRPT PIC18F8XJ72 ALRMVALH PIC18F8XJ72 ALRMVALL PIC18F8XJ72 CTMUCONH PIC18F8XJ72 ...
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... NOP instruction). The PIC18F87J72 family has a Flash program memory size of 128 Kbytes (65,536 single-word instructions). The program memory maps for individual family members are shown in Figure 6-1. ...
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... Words, CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices in the PIC18F87J72 family are shown in Table 6-1. Their location in the memory map is shown with the other memory vectors in Figure 6-2. Additional details on the device Configuration Words are provided in Section 26.1 “ ...
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... Microchip Technology Inc. PIC18F87J72 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... PIC18F87J72 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 6.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F87J72 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
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... ADDWF 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... The memory space is divided into as many as 16 banks that contain 256 bytes each. PIC18F86J72 and PIC18F87J72 devices implement all 16 complete banks, for a total of 4 Kbytes. Figure 6-6 and Figure 6-7 show the data memory organization for the devices. ...
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... FIGURE 6-6: DATA MEMORY MAP FOR PIC18F86J72 AND PIC18F87J72 DEVICES BSR<3:0> = 0000 Bank 0 = 0001 Bank 1 = 0010 Bank 2 = 0011 Bank 3 = 0100 Bank 4 = 0101 Bank 5 = 0110 Bank 6 = 0111 Bank 7 = 1000 Bank 8 = 1001 Bank 9 = 1010 Bank 10 = 1011 Bank 11 = 1100 Bank 12 = 1101 Bank 13 = 1110 Bank 14 ...
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... PIC18F87J72 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 6-2 and Table 6-3. TABLE 6-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J72 FAMILY DEVICES Name Name Addr. Addr. ...
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... PIC18F87J72 FAMILY TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY File Name Bit 7 Bit 6 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 LCDREG — CPEN BIAS2 WDTCON REGSLP — RCON IPEN — TMR1H ...
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... PIC18F87J72 FAMILY TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 SPBRG1 EUSART Baud Rate Generator Low Byte RCREG1 EUSART Receive Register TXREG1 EUSART Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN LCDPS WFT BIASMD LCDA ...
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... TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 SPBRGH1 EUSART Baud Rate Generator High Byte BAUDCON1 ABDOVF RCMT RXDTP LCDDATA22 — — LCDDATA21 S31C3 S30C3 S29C3 LCDDATA20 S23C3 S22C3 S21C3 LCDDATA19 S15C3 S14C3 S13C3 LCDDATA18 S07C3 S06C3 ...
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... PIC18F87J72 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled ...
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... Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The Access RAM bit, ‘a’, determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 6.3.1 “Bank Select Register”) are used with the address to determine the complete 12-bit address of the register. When ‘ ...
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... PIC18F87J72 FAMILY 6.4.3.1 FSR Registers and the INDF Operand At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations ...
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... PIC18F87J72 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 000h 060h Bank 0 100h Bank 1 through Bank 14 F00h ...
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... PIC18F87J72 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “ ...
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... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F87J72 FAMILY FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. ...
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... Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC18F87J72 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... MOVWFWORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWFWORD_ODD 2010 Microchip Technology Inc. PIC18F87J72 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F87J72 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1,024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1,024 bytes of program memory is erased ...
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... Note 1: Unlike previous PIC18 Flash devices, members of the PIC18F87J72 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence ...
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... PIC18F87J72 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...
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... FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING). The PIC18F87J72 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1 ...
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... PIC18F87J72 FAMILY 7.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.4 UNEXPECTED TERMINATION OF ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2010 Microchip Technology Inc. PIC18F87J72 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8-2: ...
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... PIC18F87J72 FAMILY Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L RES3:RES0 = 16 (ARG1H ARG2H (ARG1H ARG2L (ARG1L ARG2H 2 (ARG1L ...
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... INTERRUPTS Members of the PIC18F87J72 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
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... PIC18F87J72 FAMILY FIGURE 9-1: PIC18F87J72 FAMILY INTERRUPT LOGIC PIR1<6:3,1:0> PIE1<6:3,1:0> IPR1<6:3,1:0> PIR2<7:6,3:1> PIE2<7:6 3:1> IPR2<7:6,3:1> PIR3<6:0> PIE3<6:0> IPR3<6:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<6:3,1:0> PIE1<6:3,1:0> IPR1<6:3,1:0> PIR2<7:6,3:1> PIE2<7:6,3:1> IPR2<7:6,3:1> PIR3<6:0> PIE3<6:0> IPR3<6:0> DS39979A-page 90 TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF ...
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... A mismatch condition will continue to set this bit. Reading PORTB, then waiting one instruction cycle, will end the mismatch condition and allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... PIC18F87J72 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 R/W-0 ...
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... PIC18F87J72 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F87J72 FAMILY U-0 R/W-0 R/W-0 — BCLIF LVDIF U = Unimplemented bit, read as ‘0’ ...
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... PIC18F87J72 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 R/W-0 R-0 — LCDIF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected) ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 U-0 TX1IE SSPIE — ...
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... PIC18F87J72 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 OSCFIE CMIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit ...
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... CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 0 RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R-0 R/W-0 R/W-0 TX2IE CTMUIE CCP2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F87J72 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC18F87J72 FAMILY U-0 R/W-1 R/W-1 — BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F87J72 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 R/W-1 R-1 — LCDIP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected) ...
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... For details of bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
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... PIC18F87J72 FAMILY 9.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
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... RD TRIS PORT 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
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... PIC18F87J72 FAMILY TABLE 10-2: OUTPUT DRIVE LEVELS FOR VARIOUS PORTS Low Medium PORTA<5:0> PORTD PORTA<7:6> PORTF PORTE PORTB PORTG PORTC 10.1.3 PULL-UP CONFIGURATION Four of the I/O ports (PORTB, PORTD, PORTE and PORTJ) implement configurable weak pull-ups on all pins. These are internal pull-ups that allow floating digital input signals to be pulled to a consistent level without the use of external resistors ...
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... Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘x’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O Type O DIG LATA< ...
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... PIC18F87J72 FAMILY 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only and tolerate voltages up to 5.5V. EXAMPLE 10-2: INITIALIZING PORTB ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O Type ...
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... PIC18F87J72 FAMILY TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB7 LATB6 TRISB TRISB7 TRISB6 TRISB5 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTCON3 INT2IP INT1IP LCDSE1 SE15 SE14 LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTB. ...
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... Note: These pins are configured as digital inputs on any device Reset. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. ...
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... PIC18F87J72 FAMILY TABLE 10-7: PORTC FUNCTIONS TRIS Pin Name Function I/O Setting RC0/T1OSO/ RC0 O 0 T13CKI 1 I T1OSO O x T13CKI I 1 RC1/T1OSI/ RC1 O 0 CCP2/SEG32 I 1 T1OSI I x (1) CCP2 SEG32 O x RC2/CCP1/ RC2 O 0 SEG13 I 1 CCP1 SEG13 O x RC3/SCK/SCL/ RC3 ...
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... CCP2OD CCP1OD LCDSE1 SE15 SE14 LCDSE2 SE23 SE22 LCDSE3 SE31 SE30 LCDSE4 — — Legend: Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 TRISC4 ...
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... PIC18F87J72 FAMILY 10.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. All pins on PORTD are digital only and tolerate voltages up to 5.5V. All pins on PORTD are implemented with Schmitt Trigger input buffers ...
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... LATD6 TRISD TRISD7 TRISD6 PORTG RDPU REPU LCDSE0 SE07 SE06 Legend: Shaded cells are not used by PORTD. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD<0> data input. O ANA LCD Segment 0 output; disables all other pin functions. ...
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... PIC18F87J72 FAMILY 10.6 PORTE, TRISE and LATE Registers PORTE is a 7-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISE and LATE. All pins on PORTE are digital only and tolerate voltages up to 5.5V. All pins on PORTE are implemented with Schmitt Trigger input buffers ...
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... REPU TRISG SPIOD CCP2OD CCP1OD LCDCON LCDEN SLPEN LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTE. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O Type O DIG LATE<0> data output PORTE<0> data input. I ANA LCD module bias voltage input. ...
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... PIC18F87J72 FAMILY 10.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). 2010 Microchip Technology Inc. PIC18F87J72 FAMILY I/O I/O Type ...
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... PIC18F87J72 FAMILY TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 PORTF RF7 RF6 LATF LATF7 LATF6 TRISF TRISF7 TRISF6 TRISF5 ADCON1 TRIGSEL — CMCON C2OUT C1OUT CVRCON CVREN CVROE LCDSE2 SE23 SE22 LCDSE3 SE31 SE30 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. ...
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... TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Although the port itself is only five bits wide, the PORTG<7:5> bits are still implemented to control the weak pull-ups on the I/O ports associated with PORTD, PORTE and PORTJ ...
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... PIC18F87J72 FAMILY TABLE 10-16: PORTG FUNCTIONS TRIS Pin Name Function Setting RG0/LCDBIAS0 RG0 0 1 LCDBIAS0 x RG1/TX2/CK2 RG1 0 1 TX2 1 CK2 1 1 RG2/RX2/DT2/ RG2 LCAP 1 RX2 1 DT2 LCAP RG3/V 2 RG3 0 LCAP LCAP RG4/SEG26/ RG4 0 RTCC 1 SEG26 x RTCC x Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Don’ ...
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... Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
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... PIC18F87J72 FAMILY 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 11.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 126 Preliminary 2010 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F87J72 FAMILY 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM (8-BIT MODE) ...
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... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Oscillator Freq. Type LP 32.768 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F87J72 FAMILY 12.3.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
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... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 132 Preliminary 2010 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... PIC18F87J72 FAMILY 13.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 2010 Microchip Technology Inc. PIC18F87J72 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. The Timer3 module is controlled through the T3CON register (Register 14-1) ...
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... PIC18F87J72 FAMILY 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 14-1: TIMER3 BLOCK DIAGRAM (8-BIT MODE) Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS<1:0> T3SYNC TMR3ON CCPx Special Event Trigger CCPx Select from T3CON<6,3> ...
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... T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 138 Preliminary 2010 Microchip Technology Inc. ...
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... Timer1 Oscillator Internal RC Alarm Event 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The RTCC module is intended for applications, where accurate time must be maintained for an extended period with minimum to no intervention from the CPU. The module is optimized for low-power usage in order to provide extended battery life while keeping track of time ...
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... PIC18F87J72 FAMILY 15.1 RTCC MODULE REGISTERS The RTCC module registers are divided into following categories: RTCC Control Registers • RTCCFG • RTCCAL • PADCFG1 • ALRMCFG • ALRMRPT RTCC Value Registers • RTCVALH and RTCVALL – Can access the fol- lowing registers ...
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... The RTCCFG register is only affected by a POR. For Resets other than POR, RTCC will continue to run even if the device is in Reset write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY (1) R-0 R-0 R/W-0 (3) RTCSYNC HALFSEC RTCOE U = Unimplemented bit, read as ‘ ...
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... PIC18F87J72 FAMILY REGISTER 15-2: RTCCAL: RTCC CALIBRATION REGISTER R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute ...
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... The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVALH ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVALL ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 AMASK0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th , once every four years) Preliminary R/W-0 ...
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... PIC18F87J72 FAMILY REGISTER 15-5: ALRMRPT: ALARM CALIBRATION REGISTER R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ...
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... Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY (1) R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 U = Unimplemented bit, read as ‘ ...
Page 146
... PIC18F87J72 FAMILY REGISTER 15-11: HOUR: HOUR VALUE REGISTER U-0 U-0 R/W-x — — HRTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from ...
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... Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from Note 1: A write to this register is only allowed when RTCWREN = 1. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY (1) R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 MTHONE2 U = Unimplemented bit, read as ‘ ...
Page 148
... PIC18F87J72 FAMILY REGISTER 15-17: ALRMHR: ALARM HOURS VALUE REGISTER U-0 U-0 R/W-x — — HRTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from ...
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... FIGURE 15-3: ALARM DIGIT FORMAT Hours (24-hour format) 0-2 0-9 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 15.2 Operation 15.2.1 REGISTER INTERFACE The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format. This simplifies the firmware when using the module, as each of the digits is contained within its own 4-bit value (see Figure 15-2 and Figure 15-3) ...
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... PIC18F87J72 FAMILY 15.2.2 CLOCK SOURCE As mentioned earlier, the RTCC module is intended to be clocked by an external Real-Time Clock crystal oscillating at 32.768 kHz, but can also be an internal oscillator. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L<1>). FIGURE 15-4: CLOCK SOURCE MULTIPLEXING 32 ...
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... If the two values matched, then a rollover did not occur. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 15.2.7 WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RTCCFG<5>) must be set. ...
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... PIC18F87J72 FAMILY TABLE 15-4: ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMPTR<1:0> ALRMVALH ALRMMIN 00 ALRMWD 01 ALRMMNTH 10 — 11 15.2.9 CALIBRATION The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than three seconds per month ...
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... ALRMRPT register with FFh. After each alarm is issued, the ALRMRPT register is decremented by one. Once the register has reached ‘00’, the alarm will be issued one last time. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Day of the Week Month Day d ...
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... PIC18F87J72 FAMILY 15.3.2 ALARM INTERRUPT At every alarm event, an interrupt is generated. Addi- tionally, an alarm pulse output is provided that operates at half the frequency of the alarm. The alarm pulse output is completely synchronous with the RTCC clock and can be used as a trigger clock to other peripherals. This output is available on the RTCC pin ...
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... ALRMVALH Alarm Value High Register Window Based on ALRMPTR<1:0> ALRMVALL Alarm Value Low Register Window Based on ALRMPTR<1:0> Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Bit 4 Bit 3 Bit 2 RTCSYNC HALFSEC ...
Page 156
... PIC18F87J72 FAMILY NOTES: DS39979A-page 156 Preliminary 2010 Microchip Technology Inc. ...
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... Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on a CCP1 match. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Each CCP module contains two 8-bit registers that can operate as two 8-bit Capture registers, two 8-bit Compare registers or two PWM Master/Slave Duty Cycle registers ...
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... PIC18F87J72 FAMILY 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... Capture PWM None Compare PWM None PWM Capture None PWM Compare None PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Interaction Preliminary DS39979A-page 159 ...
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... PIC18F87J72 FAMILY 16.2 Capture Mode In Capture mode, the CCPR2H:CCPR2L register pair captures the 16-bit value of the TMR1 or TMR3 register when an event occurs on the CCP2 pin (RC1 or RE7, depending on device configuration). An event is defined as one of the following: • Every falling edge • Every rising edge • ...
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... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 16.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M<3:0> = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP2IE bit is set. ...
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... PIC18F87J72 FAMILY TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN — PIR3 — LCDIF PIE3 — LCDIE IPR3 — LCDIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISC ...
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... Q clock bits of the prescaler, to create the 10-bit time base. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY A PWM output (Figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
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... PIC18F87J72 FAMILY 16.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> bits contain the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>. The following equation is ...
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... Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 166 Preliminary 2010 Microchip Technology Inc. ...
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... T13CKI Source Select INTRC Oscillator INTOSC Oscillator 2010 Microchip Technology Inc. PIC18F87J72 FAMILY The LCD driver module supports these features: • Direct driving of LCD panel • On-chip bias generator with dedicated charge pump to support a range of fixed and variable bias options • ...
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... PIC18F87J72 FAMILY 17.1 LCD Registers The LCD driver module has 33 registers: • LCD Control Register (LCDCON) • LCD Phase Register (LCDPS) • LCDREG Register (LCD Regulator Control) • Five LCD Segment Enable Registers (LCDSE4:LCDSE0) • 20 LCD Data Registers (LCDDATAx, for x from 0 to 22, with 5, 11 and 17 not implemented) 17 ...
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... Microchip Technology Inc. PIC18F87J72 FAMILY R-0 R/W-0 R/W-0 WA LP3 LP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 ...
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... PIC18F87J72 FAMILY REGISTER 17-3: LCDSEx: LCD SEGMENT ENABLE REGISTERS R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 SEG(n + 7):SEG(n): Segment Enable bits For LCDSE0 For LCDSE1 For LCDSE2 For LCDSE3 For LCDSE4 Segment function of the pin is enabled ...
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... S32C0 Note 1: Only bit<0> of these registers is implemented. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Individual LCDDATA bits are named by the convention “SxxCy”, with “xx” as the segment number and “y” as the common number. The relationship is summarized in Table 17-2. The prototype LCDDATA register is shown in Register 17-4 ...
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... PIC18F87J72 FAMILY 17.2 LCD Clock Source The LCD driver module generates its internal clock from 3 possible sources: • System clock (F /4) OSC • Timer1 oscillator • INTRC source The LCD clock generator uses a configurable divide-by-32/divide-by-8192 postscaler to produce a baseline frequency of about 1 kHz nominal, regardless of the source selected ...
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... DD on-chip LCD voltage regulator. 17.3.1 LCD BIAS TYPES PIC18F87J72 family devices support three bias types based on the waveforms generated to control segments and commons: • Static (two discrete levels) • 1/2 Bias (three discrete levels • 1/3 Bias (four discrete levels) The use of different waveforms in driving the LCD is dis- cussed in more detail in Section 17.8 “ ...
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... PIC18F87J72 FAMILY 17.3.3 BIAS CONFIGURATIONS PIC18F87J72 family devices have four distinct circuit configurations for LCD bias generation: • M0: Regulator with Boost • M1: Regulator without Boost • M2: Resistor Ladder with Software Contrast • M3: Resistor Ladder with Hardware Contrast 17.3.3.1 M0 (Regulator with Boost operation, the LCD charge pump feature is enabled ...
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... Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer based on the actual LCD specifications. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY configuration of the resistor ladder. Most applications using M2 will use a 1/3 or 1/2 Bias type. While Static ...
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... PIC18F87J72 FAMILY 17.3.3.4 M3 (Hardware Contrast) In M3, the LCD regulator is completely disabled. Like M2, LCD bias levels are tied and are generated DD using an external divider. The difference is that the inter- nal voltage reference is also disabled and the bottom of the ladder is tied to ground (V ); see Figure 17-5. The ...
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... LCDBIAS pins can be changed to increase or decrease current. As always, any changes should be evaluated in the actual circuit for its impact on the application. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 17.4 LCD Multiplex Types The LCD driver module can be configured into four multiplex types: • ...
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... PIC18F87J72 FAMILY 17.7 LCD Frame Frequency The rate at which the COM and SEG outputs change is called the LCD frame frequency. Frame frequency is set by the LP<3:0> bits (LCDPS<3:0>) and is also affected by the Multiplex mode being used. The rela- tionship between the Multiplex mode, LP bits setting and frame rate is shown in Table 17-4 and Table 17-5 ...
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... FIGURE 17-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 SEG0 SEG1 COM0-SEG0 COM0-SEG1 1 Frame Preliminary DS39979A-page 179 ...
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... PIC18F87J72 FAMILY FIGURE 17-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 180 COM0 COM1 SEG0 SEG1 1 Frame Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 17-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39979A-page 181 ...
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... PIC18F87J72 FAMILY FIGURE 17-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 182 COM0 COM1 SEG0 SEG1 1 Frame Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 17-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39979A-page 183 ...
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... PIC18F87J72 FAMILY FIGURE 17-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 184 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame 2010 Microchip Technology Inc. ...
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... FIGURE 17-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 COM2 SEG0 SEG1 Preliminary Frames DS39979A-page 185 ...
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... PIC18F87J72 FAMILY FIGURE 17-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 DS39979A-page 186 COM0 COM1 COM2 SEG0 SEG2 SEG1 COM0-SEG0 COM0-SEG1 Preliminary Frame 2010 Microchip Technology Inc. ...
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... FIGURE 17-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 COM2 SEG0 SEG1 Preliminary Frames DS39979A-page 187 ...
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... PIC18F87J72 FAMILY FIGURE 17-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39979A-page 188 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 17-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames Preliminary DS39979A-page 189 ...
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... PIC18F87J72 FAMILY 17.9 LCD Interrupts The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Writing pixel data at the frame boundary allows a visually crisp transition of the image. ...
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... COM2 SEG0 2 Frames SLEEP 2010 Microchip Technology Inc. PIC18F87J72 FAMILY internal oscillators (either INTRC or INTOSC as the default system clock). While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shutdown of the core and other peripheral functions ...
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... PIC18F87J72 FAMILY 17.11 Configuring the LCD Module The following is the sequence of steps to configure the LCD module. 1. Select the frame clock prescale using bits, LP<3:0> (LCDPS<3:0>). 2. Configure the appropriate pins to function as segment drivers using the LCDSEx registers. 3. Configure the appropriate pins as inputs using the TRISx registers ...
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... These registers or individual bits are unimplemented on PIC18F86J72 devices. Note: When the device enters Sleep mode while operating in Bias modes M1, be sure that the bias capacitors are fully discharged in order to get the lowest Sleep current. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F87J72 FAMILY NOTES: DS39979A-page 194 Preliminary 2010 Microchip Technology Inc. ...
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... MSSP module 2 is operated in SPI mode. Additional details are provided under the individual sections. 2010 Microchip Technology Inc. PIC18F87J72 FAMILY 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
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... PIC18F87J72 FAMILY 18.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I 2010 Microchip Technology Inc. PIC18F87J72 FAMILY R/W-0 R/W-0 (2) (3) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
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... PIC18F87J72 FAMILY 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... LSb MSb PROCESSOR 1 2010 Microchip Technology Inc. PIC18F87J72 FAMILY to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the SPIOD bit (TRISG<7>). Setting the bit configures both pins for open-drain operation ...
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... PIC18F87J72 FAMILY 18.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 18-2) will broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...