73M1903-IM/F Maxim Integrated Products, 73M1903-IM/F Datasheet - Page 44

• Manufacturer Part Number: 73M1903-IM/F
• Description: IC MODEM AFE V.22BIS 32-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73M1903-IM/F

• Number Of Channels: 2
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Bits: -

73M1903 Data Sheet
Example 2:
Fs = 8.0 kHz or Fvco = 2 x 2304 x 8 kHz =36.864 MHz, Fref = 2.304 MHz.
Ndvsr = Integer [Fvco/Fref] = 16 = 10h;
Nrst= 1-1 = 0 from Fvco/Fref = 16/1;
Nseq = {x,x,x,x,x,x,x,x} = xxh.
Example 3:
Fs = 9.6 kHz or Fvco = 2 x 2304 x 9.6 kHz =44.2368 MHz, Fref = 2.4576 MHz.
Ndvsr = Integer [Fvco/Fref] = 18 = 16h;
Nrst= 1-1 = 0 from Fvco/Fref = 18/1;
Nseq = {x,x,x,x,x,x,x,x} = xxh.
It is important to note that in general the NCO based feedback divider will generate a fixed jitter pattern
whose frequency components are at Fref/Accreset2 and its integer multiples. The overall jitter frequency
will be a nonlinear combination of jitters from both pre-scaler and PLL NCO. The fundamental frequency
component of this jitter is at Fref/Prst/Nrst. The PLL parameters should be selected to remove this jitter.
Three separate controls are provided to fine tune the PLL as shown in the following sections.
To ensure quick settling of PLL, a feature was designed into the 73m1903 where Ichp is kept at a higher
value until lokdet becomes active or Frcvco bit is set to 1, whichever occurs first. Thus PLL is guaranteed
to have the settling time of less than one frame synch period after a new set of NCO parameters had
been written to the appropriate registers. The serial port register writes for a particular sample rate should
be done in sequence starting from register 08h ending in register 0dh. 0dh register should be the last one
to be written to. This will be followed by a write to the next register in sequence (0eh) to force the
transition of Sysclk from Xtal to Pllclk.
Upon the system reset, the system clock is reset to Fxtal/9. The system clock will remain at Fxtal/9 until
the host forces the transition, but no sooner the second frame synch period after the write to 0dh. When
this happens, the system clock will transition to pllclk without any glitches through a specially designed
deglitch mux.
Examples of NCO Settings
Example 1:
Crystal Frequency = 24.576 MHz; Desired Sampling Rate, Fs = 13.714 kHz(=2.4 kHz x 10/7 x 4)
Step 1. First compute the required VCO frequency, Fvco, corresponding to
Fs = 2.4 kHz x 10/7 x 4 = 13.714 kHz, or
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 10/7 x 4 = 63.19543 MHz.
Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers.
This is initially given by:
After a few rounds of simplification this ratio reduces to:
44
Fvco
Fvco
=
/
/
Fxtal
Fxtal
=
=
Dnco1
Nnco2
Dnco2
Nnco1
18
7
2
•
2304
=
24
•
(
2.4kHz
.
576
=
MHz
1
7
•
10/7
•
)
•
4
18
(
1
7
1
18
1
.
)
DS_1903_032
Rev. 2.1