XC3S500E-4FG320I Xilinx Inc, XC3S500E-4FG320I Datasheet - Page 220

• Manufacturer Part Number: XC3S500E-4FG320I
• Description: IC FPGA SPARTAN 3E 320FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FG320I

• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 232
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 320-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pinout Descriptions
Table 152: FG400 Package Pinout (Continued)
220
Bank
GND
GND
GND
GND
GND
GND
GND
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L24P_3
IO_L25N_3
IO_L25P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3/VREF_3
IO_L28P_3
IO_L29N_3
IO_L29P_3
IO_L30N_3
IO_L30P_3
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP/VREF_3
IP/VREF_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
C18
A11
A20
B14
W1
R5
R2
R4
R3
U1
U3
G1
G6
H1
M2
N5
H4
U2
C3
P1
P5
T2
T1
T3
V1
V2
F5
L5
L8
P3
T4
K5
P6
E2
P4
A1
B7
J5
L2
L6
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VREF
VREF
VREF
Type
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 152: FG400 Package Pinout (Continued)
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
VCCAUX TDO
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S1200E
XC3S1600E
Pin Name
DS312-4 (v3.8) August 26, 2009
Product Specification
FG400
W14
Ball
D10
G12
G19
M10
M12
N13
R15
U11
D17
F15
K10
K12
K17
P19
V18
Y10
Y20
V17
B19
J11
L11
L13
L20
W7
G2
H8
R6
C2
F6
K1
K8
P2
P9
V3
Y1
B3
J9
L4
L9
CONFIG
CONFIG
JTAG
JTAG
JTAG
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R