XA6SLX25T-3FGG484Q Xilinx Inc, XA6SLX25T-3FGG484Q Datasheet - Page 6

• Manufacturer Part Number: XA6SLX25T-3FGG484Q
• Description: IC FPGA SPARTAN 6 484FGGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan®-6r

Specifications of XA6SLX25T-3FGG484Q

• Number Of Logic Elements/cells: 24051
• Number Of Labs/clbs: 1879
• Total Ram Bits: 958464
• Number Of I /o: 250
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Digital Signal Processing—DSP48A1 Slice
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All XA
Spartan-6 FPGAs have many dedicated, full-custom, low-power DSP slices, combining high speed with small size, while
retaining system design flexibility.
Each DSP48A1 slice consists of a dedicated 18 × 18 bit two’s complement multiplier and a 48-bit accumulator, both capable
of operating at up to 287 MHz. The DSP48A1 slice provides extensive pipelining and extension capabilities that enhance
speed and efficiency of many applications, even beyond digital signal processing, such as wide dynamic bus shifters,
memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The accumulator can also be
used as a synchronous up/down counter. The multiplier can perform barrel shifting.
Input/Output
The number of I/O pins varies from 132 to 316, depending on device and package size. Each I/O pin is configurable and can
comply with a large number of standards, using up to 3.3V. The Spartan-6 FPGA SelectIO Resources User Guide describes
the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins,
all other package pins have the same I/O capabilities, constrained only by certain banking rules. All user I/O is bidirectional;
there are no input-only pins.
All I/O pins are organized in four banks. Each bank has several common V
powers certain input buffers. Some single-ended input buffers require an externally applied reference voltage (V
are several dual-purpose V
pin in that bank must be connected to the same voltage rail and can not be used as an I/O pin.
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure, driving High towards V
ground, and can be put into high-Z state. Many I/O features are available to the system designer to optionally invoke in each
I/O in their design, such as weak internal pull-up and pull-down resistors, strong internal split-termination input resistors,
adjustable output drive-strengths and slew-rates, and differential termination resistors. See the Spartan-6 FPGA SelectIO
Resources User Guide for more details on available options for each I/O standard.
I/O Logic
Input and Output Delay
This section describes the available logic resources connected to the I/O interfaces. All inputs and outputs can be configured
as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input or output can
be individually delayed by up to 256 increments of ~100 ps each. This is implemented as IODELAY2. The identical delay
value is available either for data input or output. For a bidirectional data line, the transfer from input to output delay is
automatic. The number of delay steps can be set by configuration and can also be incremented or decremented while in use.
Because these tap delays vary with supply voltage, process, and temperature, an optional calibration mechanism is built into
each IODELAY2:
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•
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DS170 (v1.0) March 2, 2010
Advance Product Specification
In the simple system synchronous case, a data input delay value that guarantees zero data hold time is inserted
automatically, without user intervention.
For source synchronous designs where more accuracy is required, the calibration mechanism can (optionally)
determine dynamically how many taps are needed to delay data by one full I/O clock cycle, and then programs the
IODELAY2 with 50% of that value, thus centering the I/O clock in the middle of the data eye.
A special mode is available only for differential inputs, which uses a phase-detector mechanism to determine whether
the incoming data signal is being accurately sampled in the middle of the eye. The results from the phase-detector logic
can be used to either increment or decrement the input delay, one tap at a time, to ensure error-free operation at very
high bit rates.
REF
-I/O pins in each bank. In a given bank, when I/O standard calls for a V
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CCO
output supply-voltage pins, which also
CCO
REF
or Low towards
voltage, each V
REF
). There
REF
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