M0516ZAN Nuvoton Technology Corporation of America, M0516ZAN Datasheet - Page 235

• Manufacturer Part Number: M0516ZAN
• Description: IC MCU 32BIT 64KB FLASH 33QFN
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M0516ZAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 33-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

™
NuMicro M051
Series Technical Reference Manual
Transmit/Receive Bit Length
The bit length of a transaction word is defined in TX_BIT_LEN bit field (SPI_CNTRL [7:3]). It can
be configured up to 32 bits length in a transfer word for transmitting and receiving.
Burst Mode
SPI controller can switch to burst mode by setting TX_NUM bit field (SPI_CNTRL [9:8]) to 0x01.
In burst mode, SPI can transmit/receive two transactions in one transfer. The SPI burst mode
waveform is shown below:
Figure 6.7-4 Two Transactions in One Transfer (Burst Mode)
LSB First
The LSB bit (SPI_CNTRL [10]) defines the data transmission either from LSB or MSB firstly to
start to transmit/receive data.
Transmit Edge
The TX_NEG bit (SPI_CNTRL [2]) defines the data transmitted out either at negative edge or at
positive edge of serial clock SPICLK.
Receive Edge
The RX_NEG bit (SPI_CNTRL [1]) defines the data received in either at negative edge or at
positive edge of serial clock SPICLK.
Publication Release Date: Sept 14, 2010
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Revision V1.2