SST89V54RD-33-C-PIE Microchip Technology, SST89V54RD-33-C-PIE Datasheet - Page 54

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SST89V54RD-33-C-PIE

Manufacturer Part Number
SST89V54RD-33-C-PIE
Description
IC MCU 8BIT 24KB FLASH 40PDIP
Manufacturer
Microchip Technology
Series
FlashFlex®r
Datasheet

Specifications of SST89V54RD-33-C-PIE

Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
8051
Core Size
8-Bit
Speed
33MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
32
Eeprom Size
8K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
SST89xxxRD
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Data Sheet
9.0 SECURITY LOCK
The security lock protects against software piracy and pre-
vents the contents of the flash from being read by unautho-
rized parties. It also protects against code corruption
resulting from accidental erasing and programming to the
internal flash memory. There are two different types of
security locks in the device security lock system: hard lock
and SoftLock.
9.1 Hard Lock
When hard lock is activated, MOVC or IAP instructions exe-
cuted from an unlocked or soft locked program address
space, are disabled from reading code bytes in hard locked
memory blocks (See Table 9-2). Hard lock can either lock
both flash memory blocks or just lock the 8 KByte flash
memory block (Block 1). All external host and IAP com-
mands except for Chip-Erase are ignored for memory
blocks that are hard locked.
9.2 SoftLock
SoftLock allows flash contents to be altered under a secure
environment. This lock option allows the user to update
program code in the soft locked memory block through in-
application programming mode under a predetermined
secure environment. For example, if Block 1 (8K) memory
block is locked (hard locked or soft locked), and Block 0
memory block is soft locked, code residing in Block 1 can
program Block 0. The following IAP mode commands
Note:
©2007 Silicon Storage Technology, Inc.
FIGURE
P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1), N = Not Locked, L = Hard locked, S = Soft locked
9-1: Security Lock Levels
UPP/LL
UPU/SS
PPU/LS
PUU/SS
UUU/NN
PPP/LL
PUP/LL
54
issued through the command mailbox register, SFCM, exe-
cuted from a Locked (hard locked or soft locked) block, can
be operated on a soft locked block: Block-Erase, Sector-
Erase, Byte-Program and Byte-Verify.
In external host mode, SoftLock behaves the same as a
hard lock.
9.3 Security Lock Status
The three bits that indicate the device security lock
status are located in SFST[7:5]. As shown in Figure 9-
1 and Table 9-1, the three security lock bits control the
lock status of the primary and secondary blocks of
memory. There are four distinct levels of security lock
status. In the first level, none of the security lock bits
are programmed and both blocks are unlocked. In the
second level, although both blocks are now locked and
cannot be programmed, they are available for read
operation via Byte-Verify. In the third level, three differ-
ent options are available: Block 1 hard lock / Block 0
SoftLock, SoftLock on both blocks, and hard lock on
both blocks. Locking both blocks is the same as Level
2, Block 1 except read operation isn’t available. The
fourth level of security is the most secure level. It
doesn’t allow read/program of internal memory or boot
from external memory. For details on how to program
the security lock bits refer to the external host mode
and in-application programming sections.
SST89V54RD2/RD / SST89V58RD2/RD
UUP/LS
UPP/LL
Level 1
Level 2
Level 3
Level 4
1255 F29.0
FlashFlex MCU
S71255-10-000
12/07

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