CP2112-F01-GM Silicon Laboratories Inc, CP2112-F01-GM Datasheet - Page 14

• Manufacturer Part Number: CP2112-F01-GM
• Description: IC HID USB-TO-SMBUS BRIDGE 24QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2112-F01-GM

• Package / Case: 24-WFQFN Exposed Pad
• Applications: USB-to-SMBus Bridge
• Interface: SMBus, USB
• Voltage - Supply: 1.8V, 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Input Voltage Range (max): 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Supply Current (max): 18.5 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-2010 - KIT EVAL FOR CP2112
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-2004-5

CP2112
7. GPIO Pins
The CP2112 supports 8 user-configurable GPIO pins. Each of these GPIO pins are usable as inputs, open-drain
outputs, or push-pull outputs. Three of these GPIO pins also have alternate functions which are listed in Table 10.
By default, all of the GPIO pins are configured as a GPIO input. The pins must be configured each time the device
is reset. For example, if a device is unplugged and then plugged into a PC, the GPIO pins would be configured as
inputs and would need to be reconfigured as needed.
The difference between an open-drain output and a push-pull output is when the GPIO output is driven to logic
high. A logic high, open-drain output pulls the pin to the VIO rail through an internal, pull-up resistor. A logic high,
push-pull output directly connects the pin to the VIO voltage. Open-drain outputs are typically used when
interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to the higher, external
voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.
The speed of reading and writing the GPIO pins is subject to the timing of the USB bus. GPIO pins configured as
inputs or outputs are not recommended for real-time signalling.
7.1. GPIO.0-1—Transmit and Receive Toggle
GPIO.0 and GPIO.1 are configurable as Transmit Toggle and Receive Toggle pins. These pins are logic high when
a device is not transmitting or receiving data, and they toggle at a fixed rate as specified in Table 6 on page 6 when
data transfer is in progress. Typically, these pins are connected to two LEDs to indicate data transfer.
7.2. GPIO.7—Clock Output
GPIO.7 is configurable to output a configurable CMOS clock output. The clock output appears at the pin at the
same time the device completes enumeration and exits USB Suspend mode. The clock output is removed from the
pin when the device enters USB Suspend mode. The output frequency is configurable through the use of a divider
and the accuracy is specified in Table 6. When the divider is set to 0, the output frequency is 48 MHz. For divider
values between 1 and 255, the output frequency is determined by the formula:
14
Figure 7. Transmit and Receive Toggle Typical Connection Diagram
Equation 1. GPIO.7 Clock Output Frequency
Table 10. GPIO Pin Alternate Functions
GPIO.1 – RX Toggle
GPIO.0 – TX Toggle
GPIO.7 Clock Frequency
GPIO Pin
GPIO.0
GPIO.1
GPIO.7
CP2112
Rev. 1.0
Alternate Function
CLK Output
=
RX Toggle
TX Toggle
---------------------------------------------- -
2

ClockDivider
48 MHz
VIO