WM9705SEFT/V Wolfson Microelectronics, WM9705SEFT/V Datasheet - Page 20

• Manufacturer Part Number: WM9705SEFT/V
• Description: Audio CODECs Stereo AC'97 Codec T/P Interface
• Manufacturer: Wolfson Microelectronics

Specifications of WM9705SEFT/V

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 48 KSPS
• Interface Type: AC97
• Resolution: 12 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM9705
VARIABLE SAMPLE RATE SUPPORT
SPDIF OR I
w
2
S DIGITAL AUDIO DATA OUTPUT
enhancement applied. It can also be bypassed if desired. This function is enabled by setting the
bit POP in Register 20h.
The DACs and ADCs on this device support all the recommended sample rates specified in the
Intel AC’97 rev2.1 and rev2.2 specifications for audio rates. The default rate is 48ks/s. If
alternative rates are selected and variable rate audio is enabled (Register 2Ah, bit 0), the AC’97
interface continues to run at 48k words per second, but data is transferred across the link in
bursts such that the net sample rate selected is achieved. It is up to the AC’97 Revision 2.1/2
compliant controller to ensure that data is supplied to the AC link, and received from the AC link,
at the appropriate rate.
Variable rates are selected by writing to registers 2Ch (DAC) and 32h (ADC). ADC and DAC rates
may be set independently, with left and right channels always at the same rate. Note that register
2Ch should only be written to when the DAC is powered ON, similarly register 32h should only be
written to when the ADC is powered ON (see register 26h for power control). The device supports
on demand sampling. That is, when the DAC signal processing circuits need another sample, a
sample request is sent to the controller which must respond with a data sample in the next frame
it sends. For example, if a rate of 24ks/s is selected, on average the device will request a sample
from the controller every other frame, for each of the stereo DACs. Note that if an unsupported
rate is written to one of the rate registers, the rate will default to the nearest rate supported. The
Register will then respond, when interrogated, with the supported rate the device has defaulted to.
The WM9705 clocks will scale automatically dependent upon the MCLK frequency, where MCLK
is not equal to 24.576MHz. With a 24MHz clock the BCLK frequency expected will be 12MHz and
the sampling frequency (SYNC0 expected is BCLK/256 = 46.875kHz.
Table 1 Variable Sample Rates Supported
The WM9705 SPDIF output may be enabled in hardware by holding pin 44 (SPEN) high when
RESETB is taken high, or by writing to the SPDIF control bit in register 2Ah. If SPDIF pin 48 is
pulled high at start-up by a weak pull-up (e.g. 100k), then SPDIF capability bit in register 28h is
set to ‘0’, i.e. no SPDIF capability. This allows for stuffing options, so that when SPDIF external
components are not provided, the driver will see ‘no SPDIF capability’ and ‘grey out’ the relevant
boxes in the control panel.
Additionally the digital audio may be output in I
and outputting a frame clock or LRCLK onto pin 43. The data is clocked onto pin 44 using the
regular BITCLK at 256fs, which would also then be used as the MCLK if the data is taken to an
external DAC. Operation in this mode is selected by setting bit I
also available and can be output on SPDIF by setting bit I2S64 in register 74h. Note that I
operation is only supported for 48ks/s operation. Hardware selection of SPDIF operation by
pulling pin SPEN ‘hi’ is compatible with I
used to hold SPEN high at start-up. The SPEN pin becomes I
enabled, and the weak pull-up on this pin is overdriven.
For both SPDIF and I
link in the same slots as normal DAC data or may be sent in different slots. The output slots that
contain the SPDIF/I
with AC’97 rev2.2 specification with regard to slot mapping; therefore the default mode of
operation is to output SPDIF or I
slots currently in use. Alternatively if required, data may be mapped from any of the available
slots by selection using SPSA bits. The following table shows the default slot mapping for audio
DACs and SPDIF/I
SAMPLE RATE
AUDIO
11025
16000
22050
32000
44100
48000
8000
2
S data: (further details in the register description section later).
2
S data are selected by bits SPSA[1:0] in register 2Ah. WM9705 is compliant
2
S modes the data that is output may be sent from the WM9705 via the AC
CONTROL VALUE
D15-D0
7D000
2
AC44
BB80
1F40
2B11
3E80
5622
S data from the next data slots available after the audio data
2
S operation, provided a weak pull-up (circa 100k) was
2
S format using pin 44 (SPEN) as the data output,
2
S in register 5Ch. A 64fs bitclk is
2
S data output pin when I
PD Rev 4.5 July 2008
Production Data
2
S is
2
S
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