WM8731SEDS/V Wolfson Microelectronics, WM8731SEDS/V Datasheet - Page 36

• Manufacturer Part Number: WM8731SEDS/V
• Description: Audio CODECs Stereo Codec with H/P
• Manufacturer: Wolfson Microelectronics

Specifications of WM8731SEDS/V

• Interface Type: Serial (2-Wire or 3-Wire), I2S
• Resolution: 24 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC / 2 DAC
• Snr: 90 dB
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8731 / WM8731L
Figure 26 Left Justified Mode
w
DACLRC/
ADCLRC
DACDAT/
ADCDAT
BCLK
MSB
1
2
DIGITAL AUDIO INTERFACES
WM8731/L may be operated in either one of the 4 offered audio interface modes. These are:
•
•
•
•
All four of these modes are MSB first and operate with data 16 to 32 bits.
Note that 32 bit data is not supported in right justified mode.
The digital audio interface takes the data from the internal ADC digital filter and places it on the
ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital
filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls
whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are
synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. BCLK maybe an input or an output dependent on whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section
The digital audio interface also receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls
whether Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous
with the BCLK signal with each data bit transition signified by a BCLK high to low transition. DACDAT
is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is
in master or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8731/L. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR
or DACLRC transition.
I
ADCLRC transition.
2
3
S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC or
Right justified
Left justified
I
DSP mode
2
S
LEFT CHANNEL
n-2 n-1
n
LSB
MSB
1/fs
1
2
3
RIGHT CHANNEL
n-2 n-1
n
LSB
PD, Rev 4.8, April 2009
Production Data
36