CS8427-CZZ Cirrus Logic Inc, CS8427-CZZ Datasheet - Page 8

• Manufacturer Part Number: CS8427-CZZ
• Description: Audio DSPs 96 kHz Digital Audio Transceiver
• Manufacturer: Cirrus Logic Inc

Specifications of CS8427-CZZ

• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6.3 mA to 76.6 mA
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Input Voltage: 4.8 V to 5.8 V
• Package / Case: TSSOP-28
• Rohs Compliant: Yes
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: TSSOP
• No. Of Pins: 28
• Supply Voltage Max: 5.5V
• Supply Voltage Min: 4.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
Notes: 8. The active edges of ISCLK and OSCLK are programmable.
8
OSCLK Active Edge to SDOUT Output Valid
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
O/RMCK to I/OSCLK active edge delay
O/RMCK to I/OLRCK delay
I/OSCLK and I/OLRCK Duty Cycle
Slave Mode
I/OSCLK Period
I/OSCLK Input Low Width
I/OSCLK Input High Width
I/OSCLK Active Edge to I/OLRCK Edge
I/OLRCK Edge Setup Before I/OSCLK Active Edge
(o u tp u t)
O L R C K
(o u tp u t)
(o u tp u t)
(o u tp u t)
O S C L K
O M C K
IS C L K
IL R C K
R M C K
R M C K
(in p u t)
10. The polarity of ILRCK and OLRCK is programmable.
11. No more than 128 SCLK per frame.
12. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
13. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has
Figure 1. Audio Port Master Mode Timing
9. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising
H a rd w a re M o d e
edge. When these signals are derived from RMCK, they are clocked from its falling edge.
has changed.
changed.
S o ftw a re M o d e
t s m d
Parameter
t
lm d
L
= 20 pF.
(Note 8, 10, 12)
(Note 8, 10, 13)
(Note 8, 9)
(Note 10)
(Note 11)
(Note 8)
(Note 8)
(Note 8)
ISCLK
OSCLK
ILRCK
OLRCK
(input)
SDOUT
(input)
Figure 2. Audio Port Slave Mode and Data Input Timing
SDIN
Symbol
t
t
t
t
t
t
t
t
sckw
sckh
lrckd
lrcks
smd
t
t
sckl
dpd
lmd
dh
ds
t
lrckd
Min
20
20
36
14
14
20
20
t
0
0
-
-
lrcks
t
ds
Typ
50
-
-
-
-
-
-
-
-
-
-
t
sckh
t
dh
t
Max
sckw
20
10
10
-
-
-
-
-
-
-
-
t
sckl
t dpd
CS8427
DS477F5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%