SI7860DP-T1-E3 Vishay, SI7860DP-T1-E3 Datasheet
SI7860DP-T1-E3
Specifications of SI7860DP-T1-E3
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SI7860DP-T1-E3 Summary of contents
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... Bottom View Ordering Information: Si7860DP-T1 Si7860DP-T1-E3 (Lead (Pb)-free) Si7860DP-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS T Parameter Drain-Source Voltage Gate-Source Voltage a Continuous Drain Current (T = 150 °C) J Pulsed Drain Current Continuous Source Current (Diode Continuous) Avalanche Current Single Pulse Avalanche Energy a Maximum Power Dissipation ...
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... Si7860DP Vishay Siliconix SPECIFICATIONS °C, unless otherwise noted J Parameter Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current a On-State Drain Current a Drain-Source On-State Resistance a Forward Transconductance a Diode Forward Voltage b Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance ...
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... Document Number: 71854 S09-0222-Rev. E, 09-Feb-09 2500 2000 1500 1000 2.00 1.75 1.50 1.25 1.00 0.75 0. 0.040 0.032 0.024 0.016 °C J 0.008 0.000 0.8 1.0 1.2 Si7860DP Vishay Siliconix C iss C oss 500 C rss Drain-to-Source Voltage (V) DS Capacitance 100 T - Junction Temperature (°C) J On-Resistance vs. Junction Temperature ...
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... Si7860DP Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0 250 µA D 0.3 0.0 - 0.3 - 0 Temperature (°C) J Threshold Voltage 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0. Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 ...
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... TYP. 3.98 TYP. 6.15 6.25 5.89 5.99 3.66 3.84 3.78 3.91 0.75 TYP. 1.27 BSC 1.27 TYP 0.61 0.71 0.61 0.71 0.13 0.20 - 12° 0.25 0.36 0.125 TYP. Package Information Vishay Siliconix Backside View of Single Pad Backside View of Dual Pad INCHES MIN ...
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... The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Sili- conix MOSFETs. Click on the PowerPAK SO-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package ...
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... Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this doc- ument. The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the Pow- erPAK SO-8 dual package ...
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... No significant effect was observed Si7446DP 41 36 100 10000 0.00 Figure 6. Spreading Copper Junction-to-Ambient Performance AN821 Vishay Siliconix R vs. Spreading Copper 100 % Back Copper) 100 % 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2 ...
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... AN821 Vishay Siliconix SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8 In any design, one must take into account the change in MOSFET r with temperature (Figure 7). DS(on) On-Resistance vs. Junction Temperature 1 1 1.4 1.2 1.0 0.8 0 Junction Temperature (°C) J Figure 7. MOSFET r vs. Temperature DS(on) A MOSFET generates internal heat due to the current passing through the channel ...
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... RECOMMENDED MINIMUM PADS FOR PowerPAK 0.024 (0.61) 0.026 (0.66) 0.050 (1.27) Return to Index Return to Index Document Number: 72599 Revision: 21-Jan-08 ® SO-8 Single 0.260 (6.61) 0.150 (3.81) 0.032 (0.82) Recommended Minimum Pads Dimensions in Inches/(mm) Application Note 826 Vishay Siliconix 0.040 (1.02) www.vishay.com 15 ...
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... Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part ...