74AUP1G58L6X Fairchild Semiconductor, 74AUP1G58L6X Datasheet - Page 10

• Manufacturer Part Number: 74AUP1G58L6X
• Description: Gates (AND / NAND / OR / NOR) 2 Input, Low Power Config. Logic Gate
• Manufacturer: Fairchild Semiconductor

Specifications of 74AUP1G58L6X

• Product: Configurable
• Logic Family: TinyLogic
• Propagation Delay Time: 1.3 ns to 3.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: Micropak-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2008 Fairchild Semiconductor Corporation
74AUP1G58 • Rev. 1.0.5
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
FHX
5X
DETAIL A
PIN 1
MIN 250uM
(0.08) 4X
2X
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
E. DRAWING FILENAME AND REVISION: MGF06AREV3
NOTES:
0.35
0.25
DESIGN.
0.05 C
C
0.35
Figure 12.
1
6
Leader (Start End)
BOTTOM VIEW
Trailer (Hub End)
TOP VIEW
SIDE VIEW
Tape Section
1.00
5
2
Carrier
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
3
4
0.60
0.55MAX
B
(0.08)
4X
0.09
0.19
1.00
A
0.05 C
6X
2X
Cavity Number
.05 C
125 (Typical)
0.10
10
75 (Typical)
0.05 C
5000
C B A
5X
1X
5X 0.40
CHAMFER
1X 0.45
0.075X45°
0.52
0.57
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
Cavity Status Cover Type Status
(0.05) 6X
DETAIL A
PIN 1 LEAD SCALE: 2X
0.90
Empty
Empty
0.20 6X
0.89
Filled
6X 0.19
0.35
0.35
0.73
0.66
0.40
0.30
Sealed
Sealed
Sealed
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