DS3065WP-100IND+ Maxim Integrated Products, DS3065WP-100IND+ Datasheet - Page 13

• Manufacturer Part Number: DS3065WP-100IND+
• Description: NVRAM 3.3V 8MB NONVOLATILE SRAM W/CLK
• Manufacturer: Maxim Integrated Products

Specifications of DS3065WP-100IND+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DS3030W executes an RTC read cycle whenever
CE (SRAM chip enable) and WE (write enable) are
inactive (high) and CS (RTC chip select) is active (low).
The least significant 4 address inputs (A0 to A3) define
which of the 16 RTC registers is to be accessed (see
Table 2). Valid data is available to the eight data output
drivers within t
input signal is stable, providing that CS and OE (output
enable) access times are also satisfied. If CS and OE
access times are not satisfied, then data access must
be measured from the later occurring signal (CS or OE)
and the limiting parameter is either t
for OE rather than address access.
The DS3030W executes an RTC write cycle whenever
CE is inactive (high) and the CS and WE signals are
active (low) after address inputs are stable. The later-
occurring falling edge of CS or WE determines the start
of the write cycle. The write cycle is terminated by the
earlier rising edge of CS or WE. All address inputs must
be kept valid throughout the write cycle. WE must return
to the high state for a minimum recovery time (t
before another cycle can be initiated. The CE and OE
control signals should be kept inactive (high) during RTC
write cycles to avoid bus contention. However, if the out-
put drivers have been enabled (CS and OE active) then
WE disables the outputs in t
The oscillator can be turned off to minimize battery cur-
rent drain. The OSC bit is the MSB of the SECONDS
register, and must be initialized to a 0 to start the oscil-
lator upon first power application. The OSC bit is facto-
ry set to a 1 prior to shipment. Oscillator operation and
frequency can be verified by setting the FT bit to a 1
and monitoring the IRQ/FT output for 512Hz.
When reading the RTC data, it is recommended to halt
updates to the external set of double-buffered RTC reg-
isters. This puts the external registers into a static state,
allowing the data to be read without register values
changing during the read process. Normal updates to
the internal registers continue while in this state.
3.3V Single-Piece 256kb Nonvolatile SRAM
ACC
(access time) after the last address
ODW
Clock Oscillator Mode
Reading the Clock
from its falling edge.
RTC Write Mode
RTC Read Mode
CO
____________________________________________________________________
for CS or t
OEC
WR
)
External updates are halted by writing a 1 to the read
bit (R). As long as a 1 remains in the R bit, updating is
inhibited. After a halt is issued, the registers reflect the
RTC count (day, date, and time) that was current at the
moment the halt command was issued. Normal
updates to the external set of registers resume within 1
second after the R bit is set to a 0 for a minimum of
500µs. The R bit must be a 0 for a minimum of 500µs to
ensure the external registers have fully updated.
As with a clock read, it is also recommended to halt
updates prior to setting new time values. Setting the
write bit (W) to a 1 halts updates of the external RTC
registers 8h to Fh. After setting the W bit to a 1, the RTC
registers can be loaded with the desired count (day,
date, and time) in BCD format. Setting the W bit to a 0
then transfers the values written to the internal registers
and allows normal clock operation to resume.
The DS3030W frequency test mode uses the IRQ/FT
open-drain output. With the oscillator running, the
IRQ/FT output toggles at 512Hz when the FT bit is a 1,
the alarm-flag enable bit (AE) is a 0, and the watchdog-
enable bit (WDS) is a 1 or the WATCHDOG register is
written to 00h (FT • AE • (WDS + WATCHDOG)). The
IRQ/FT output and the frequency test mode can be
used to measure the actual frequency of the 32.768kHz
RTC oscillator. The FT bit is reset to a 0 on power-up.
The alarm settings and control for the DS3030W reside
within RTC registers 2h–5h. The INTERRUPTS register
(6h) contains two alarm-enable bits: alarm enable (AE)
and alarm in backup enable (ABE). The AE and ABE
bits must be set as described below for the IRQ/FT out-
put to be activated when an alarm match occurs.
The alarm can be programmed to activate on a specific
day of the month or repeat every day, hour, minute, or
second. It can also be programmed to go off while the
DS3030W is in the Data Retention Mode to serve as a
system wake-up. Alarm mask bits AM1 to AM4 control
the alarm mode (see Table 3). Configurations not listed
in the table will default to the once-per-second mode to
notify the user of an incorrect alarm setting.
Using the Clock Alarm
Frequency Test Mode
with Clock
Setting the Clock
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