LCMXO256C-3TN100I Lattice, LCMXO256C-3TN100I Datasheet - Page 96

• Manufacturer Part Number: LCMXO256C-3TN100I
• Description: CPLD - Complex Programmable Logic Devices 256 LUTs 78 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LCMXO256C-3TN100I

• Memory Type: SRAM
• Number Of Macrocells: 128
• Delay Time: 4.9 ns
• Number Of Programmable I/os: 78
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 13 mA
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Programmable Type: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Current, Supply: ±10 μA
• Logic Function: Programmable
• Logic Type: CMOS
• Package Type: TQFP-100
• Special Features: Bus, In-System Programmability
• Temperature, Operating, Range: -40 to +100 °C
• Voltage, Supply: 1.8/2.5/3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
November 2006
December 2006
November 2007
February 2007
August 2007
June 2009
July 2010
Date
Version
02.3
02.4
02.5
02.6
02.7
02.8
02.9
Ordering Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Characteristics
Supplemental
Architecture
Architecture
Introduction
Information
Section
Corrections to MachXO “C” Sleep Mode Timing table - value for
t
(100ns) changed from min. to max.
Added Flash Download Time table.
EBR Asynchronous Reset section added.
Power Supply and NC table: Pin/Ball orientation footnotes added.
Updated EBR Asynchronous Reset section.
Updated sysIO Single-Ended DC Electrical Characteristics table.
Added JTAG Port Timing Waveforms diagram.
Added Thermal Management text section.
Updated title list.
Added 0.8-mm 256-pin caBGA package to MachXO Family Selection
Guide table.
Added Logic Signal Connections table for 0.8-mm 256-pin caBGA pack-
age.
Updated Part Number Description diagram and Ordering Part Number
tables with 0.8-mm 256-pin caBGA package information.
Updated sysCLOCK PLL Timing table.
WSLEEPN
7-3
(400ns) changed from max. to min. Value for t
Change Summary
MachXO Family Data Sheet
Revision History
WAWAKE