LC4064V-75TN48C Lattice, LC4064V-75TN48C Datasheet - Page 41

• Manufacturer Part Number: LC4064V-75TN48C
• Description: CPLD - Complex Programmable Logic Devices 400 MHZ 64 Macrocell 3.3 V 7.5 tPD
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4064V-75TN48C

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Number Of Product Terms Per Macro: 80
• Maximum Operating Frequency: 400 MHz
• Delay Time: 2.5 ns
• Number Of Programmable I/os: 388
• Operating Supply Voltage: 3.3 V
• Supply Current: 12 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-48
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Programmable Type: CPLD
• Voltage - Input: 3 V ~ 3.6 V
• Speed: 7.5ns
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Switching Test Conditions
Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 11.
Figure 12. Output Test Load, LVTTL and LVCMOS Standards
Table 11. Test Fixture Required Components
LVCMOS I/O, (L -> H, H -> L)
LVCMOS I/O (Z -> H)
LVCMOS I/O (Z -> L)
LVCMOS I/O (H -> Z)
LVCMOS I/O (L -> Z)
1. C
L
includes test fixtures and probe capacitance.
Test Condition
DUT
106Ω 106Ω
106Ω
106Ω
R
∞
∞
1
106Ω
106Ω
R
∞
∞
2
V
R 1
R 2
41
CCO
35pF
35pF
35pF
5pF
5pF
C
L
ispMACH 4000V/B/C/Z Family Data Sheet
1
C L
LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = V
LVCMOS 1.8 = V
1.5V
1.5V
V
V
OH
OL
+ 0.3
- 0.3
0213A/ispm4k
Timing Ref.
Point
Test
CCO
CCO
/2
/2
LVCMOS 3.3 = 3.0V
LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = 1.65V
3.0V
3.0V
3.0V
3.0V
V
CCO