LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 67

• Manufacturer Part Number: LFEC3E-5TN144C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
• Manufacturer: Lattice

Specifications of LFEC3E-5TN144C

• Number Of Logic Blocks: 384
• Number Of Macrocells: 3100
• Number Of Programmable I/os: 97
• Data Ram Size: 56320
• Delay Time: 5 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 3100
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

November 2007
Signal Descriptions
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
GSRN
NC
GND
V
V
V
V
XRES
V
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_PLL[T, C]_IN_A
[LOC][num]_PLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
[LOC]DQS[num]
Test and Programming (Dedicated pins)
TMS
TCK
CC
CCAUX
CCIOx
REF1_x,
CCPLL
V
REF2_x
Signal Name
I/O
I/O
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
LatticeECP/EC Family Data Sheet
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
Some of these user-programmable pins are shared with special function
pins. These pin when not used as special purpose pins can be programmed
as I/Os for user logic.
During configuration the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
configuration.
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
Ground. Dedicated pins.
Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. It powers all the differential and referenced input
buffers. Dedicated pins.
Power supply pins for I/O bank x. Dedicated pins.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as V
10K ohm +/-1% resistor must be connected between this pad and ground.
Power supply pin for PLL. Applicable to ECP/EC33 device.
Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be configured to be output.
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
4-1
REF
inputs. When not used, they may be used as I/O pins.
Description
Pinout Information
Pinout Information_02.5
Data Sheet