A40MX04-PLG44 Actel, A40MX04-PLG44 Datasheet - Page 36

• Manufacturer Part Number: A40MX04-PLG44
• Description: FPGA - Field Programmable Gate Array 6K System Gates
• Manufacturer: Actel

Specifications of A40MX04-PLG44

• Processor Series: A40MX04
• Core: IP Core
• Number Of Macrocells: 547
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 69
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 6000
• Package / Case: PLCC-44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on
the resistive and capacitive loading of the routing tracks,
the interconnect elements, and the module inputs being
driven. Propagation delay increases as the length of
routing tracks, the number of interconnect elements, or
the number of inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout
usually requires some paths to have longer routing
tracks.
The MX FPGAs deliver a tight fanout delay distribution,
which is achieved in two ways: by decreasing the delay of
the interconnect elements and by decreasing the number
of interconnect elements per path.
Actel’s patented antifuse offers a very low resistive/
capacitive interconnect. The antifuses, fabricated in
0.45 µm lithography, offer nominal levels of 100Ω
resistance and 7.0fF capacitance per antifuse.
MX fanout distribution is also tight due to the low
number of antifuses required for each interconnect path.
The proprietary architecture limits the number of
antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
Timing Characteristics
Device timing characteristics fall into three categories:
family-dependent,
dependent. The input and output buffer characteristics
are common to all MX devices. Internal routing delays
are device-dependent; actual delays are not determined
until after place-and-route of the user's design is
complete. Delay values may then be determined by using
the
simulation with post-layout delays.
1 -3 0
40MX and 42MX FPGA Families
Designer
software
device-dependent,
utility
or
by
and
performing
design-
v6.1
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment in Actel's Designer software prior to
placement and routing. Up to 6% of the nets in a design
may be designated as critical.
Long Tracks
Some nets in the design use long tracks, which are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and
sometimes four antifuse connections, which increase
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically, up to
6 percent of nets in a fully utilized device require long
tracks. Long tracks add approximately a 3 ns to a 6 ns
delay, which is represented statistically in higher fanout
(FO=8) routing delays in the data sheet specifications
section, shown in
Timing Derating
MX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum
processing.
minimum
temperature and worst-case processing.
operating
operating
Maximum
Table 28 on page
voltage,
temperature
timing
maximum
1-36.
parameters
and
operating
best-case
reflect