A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 11

• Manufacturer Part Number: A54SX08A-TQG100
• Description: FPGA - Field Programmable Gate Array 12K System Gates
• Manufacturer: Actel

Specifications of A54SX08A-TQG100

• Processor Series: A54SX08
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 130
• Delay Time: 4 ns to 8.4 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 8000
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Other Architectural Features
Technology
The Actel SX-A family is implemented on a high-voltage,
twin-well CMOS process using 0.22 μ / 0.25 μ design
rules. The metal-to-metal antifuse is comprised of a
combination of amorphous silicon and dielectric material
with barrier metals and has a programmed ('on' state)
resistance of 25 Ω with capacitance of 1.0 fF for low
signal impedance.
Performance
The unique architectural features of the SX-A family
enable the devices to operate with internal clock
frequencies of 350 MHz, causing very fast execution of
even complex logic functions. The SX-A family is an
optimal
functionality previously contained in multiple complex
programmable logic devices (CPLDs). In addition, designs
that previously would have required a gate array to meet
performance goals can be integrated into an SX-A device
with dramatic improvements in cost and time-to-market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
Reverse engineering is virtually impossible in SX-A
devices because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses. In
addition, since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept at device
power-up.
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
where they cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure
(Figure
Figure 1-11 • FuseLock
For more information, refer to Actel’s
Security in Actel Antifuse FPGAs
1-11).
platform
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application note.
to
Implementation of
integrate
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v5.3
I/O Modules
For a simplified I/O schematic, refer to Figure 1 in the
application note,
Each user I/O on an SX-A device can be configured as an
input, an output, a tristate output, or a bidirectional pin.
Mixed I/O standards can be set for individual pins,
though this is only allowed with the same voltage as the
input. These I/Os, combined with array registers, can
achieve clock-to-output-pad timing as fast as 3.8 ns, even
without the dedicated I/O registers. In most FPGAs, I/O
cells that have embedded latches and flip-flops,
requiring instantiation in HDL code; this is a design
complication not encountered in SX-A FPGAs. Fast pin-
to-pin timing ensures that the device is able to interface
with any other device in the system, which in turn
enables parallel design of system components and
reduces overall design time. All unused I/Os are
configured as tristate outputs by the Actel Designer
software, for maximum flexibility when designing new
boards or migrating existing designs.
SX-A I/Os should be driven by high-speed push-pull
devices with a low-resistance pull-up device when being
configured as tristate output buffers. If the I/O is driven
by a voltage level greater than V
device is NOT used, the high-resistance pull-up of the
driver and the internal circuitry of the SX-A I/O may
create a voltage divider. This voltage divider could pull
the input voltage below specification for some devices
connected to the driver. A logic '1' may not be correctly
presented in this case. For example, if an open drain
driver is used with a pull-up resistor to 5 V to provide the
logic '1' input, and V
the input signal may be pulled down by the SX-A input.
Each I/O module has an available power-up resistor of
approximately 50 kΩ that can configure the I/O in a
known state during power-up. For nominal pull-up and
pull-down resistor values, refer to
of the application note
Just slightly before V
disabled, so the I/Os will be controlled by user logic. See
Table 1-2 on page 1-8
more information concerning available I/O features.
Actel eX, SX-A, and RTSX-S
CCI
CCA
is set to 3.3 V on the SX-A device,
and
Actel eX, SX-A, and RTSX-S
reaches 2.5 V, the resistors are
Table 1-3 on page 1-8
CCI
Table 1-4 on page 1-8
and a fast push-pull
SX-A Family FPGAs
I/Os.
I/Os.
for
1-7