LFXP2-17E-5FN484I Lattice, LFXP2-17E-5FN484I Datasheet - Page 162

• Manufacturer Part Number: LFXP2-17E-5FN484I
• Description: FPGA - Field Programmable Gate Array 17K LUTs 358 I/O Ins on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-17E-5FN484I

• Number Of Macrocells: 17000
• Number Of Programmable I/os: 358
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 282624
• Number Of I /o: 358
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block
for the devices are listed in Table 10-6.
Table 10-6. True Dual Port Memory Sizes for 16K Memory for LatticeXP2
Table 10-7 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes
are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to the Appendix A.
Table 10-7. True Dual Port RAM Attributes for LatticeXP2
Port A Address depth
Port A Data Width
Port B Address depth
Port B Data Width
Port A Enable Output Registers
Port B Enable Output Registers
Enable GSR
Reset Mode
Memory File Format
Port A Write Mode
Port B Write Mode
Chip Select Decode for Port A
Chip Select Decode for Port B
Init Value
Memory Size
Dual Port
16K x 1
1K x 18
8K x 2
4K x 4
2K x 9
Attribute
Input Data
DIA[17:0]
DIA[1:0]
DIA[3:0]
DIA[8:0]
Port A
DIA
Address Depth Port A
Data Word Width Port A
Address Depth Port B
Data Word Width Port B
Register Mode
(Pipelining) for Port A
Register Mode
(Pipelining) for Port B
Enables Global Set Reset ENABLE, DISABLE
Selects the Reset type
Read / Write Mode for
Port A
Read / Write Mode for
Port B
Chip Select Decode for
Port A
Chip Select Decode for
Port B
Initialization value
Input Data
DIB[17:0]
DIB[1:0]
DIB[3:0]
DIB[8:0]
Description
Port B
DIB
Output Data
DOA[17:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
Port A
10-12
DOA
16K, 8K, 4K, 2K, 1K
1, 2, 4, 9, 18
16K, 8K, 4K, 2K, 1K
1, 2, 4, 9, 18
NOREG, OUTREG
NOREG, OUTREG
ASYNC, SYNC
BINARY, HEX,
ADDRESSED HEX
NORMAL, WRITE-
THROUGH
NORMAL, WRITE-
THROUGH
0b000, 0b001, 0b010,
0b011, 0b100, 0b101,
0b110, 0b111
0b000, 0b001, 0b010,
0b011, 0b100, 0b101,
0b110, 0b111
0x00000000000000000000
0000000000000000000000
0000000000000000000000
0000000000000000......0xF
FFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFF
Values
Output Data
DOB[17:0]
DOB[1:0]
DOB[3:0]
DOB[8:0]
Port B
DOB
LatticeXP2 Memory Usage Guide
00000000000
00000000000
00000000000
00000000000
00000000000
00000000000
0x000000000
Address Port A
NORMAL
NORMAL
ENABLE
NOREG
NOREG
[MSB:LSB]
ASYNC
Default
0b000
0b000
00000
ADA[13:0]
ADA[12:0]
ADA[11:0]
ADA[10:0]
Value
ADA[9:0]
1
1
Through IPexpress
User Selectable
Address Port B
[MSB:LSB]
ADB[13:0]
ADB[12:0]
ADB[11:0]
ADB[10:0]
ADB[9:0]
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO