AGL400V2-FGG144 Actel, AGL400V2-FGG144 Datasheet - Page 59

• Manufacturer Part Number: AGL400V2-FGG144
• Description: FPGA - Field Programmable Gate Array 400K System Gates
• Manufacturer: Actel

Specifications of AGL400V2-FGG144

• Processor Series: AGL400
• Core: IP Core
• Number Of Logic Blocks: 12
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 97
• Data Ram Size: 54 Kbit
• Supply Voltage (max): 1.5 V
• Supply Current: 27 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 400 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Drive Strength
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Note:
Drive Strength
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to
Drive Strength
4 mA
6 mA
8 mA
12 mA
16 mA
Note:
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Applicable to Advanced I/O Banks
Commercial-Case Conditions: T
Applicable to Advanced I/O Banks
Commercial-Case Conditions: T
Applicable to Standard Plus Banks
Applies to 1.2 V DC Core Voltage
Speed Grade t
Speed Grade t
Speed Grade t
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
DOUT
1.55
1.55
1.55
1.55
1.55
1.55
DOUT
1.55
1.55
1.55
1.55
1.55
1.55
DOUT
1.55
1.55
1.55
1.55
1.55
5.12 0.26 0.98
4.38 0.26 0.98
4.38 0.26 0.98
3.85 0.26 0.98
3.69 0.26 0.98
3.61 0.26 0.98
3.33 0.26 0.98
2.91 0.26 0.98
2.91 0.26 0.98
2.67 0.26 0.98
2.63 0.26 0.98
2.65 0.26 0.98
4.56 0.26 0.97
3.84 0.26 0.97
3.84 0.26 0.97
3.35 0.26 0.97
3.35 0.26 0.97
t
t
t
DP
DP
DP
J
J
J
t
t
t
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
DIN
DIN
DIN
t
t
t
PY
PY
PY
R ev i si o n 1 8
t
t
t
EOUT
1.10
1.10
1.10
1.10
1.10
1.10
EOUT
1.10
1.10
1.10
1.10
1.10
1.10
EOUT
1.10
1.10
1.10
1.10
1.10
Table 2-7 on page 2-7
5.20 4.46 2.81 3.02 10.99 10.25
4.45 3.93 3.07 3.48 10.23
4.45 3.93 3.07 3.48 10.23
3.91 3.53 3.24 3.77
3.75 3.44 3.28 3.84
3.67 3.46 3.33 4.13
3.38 2.75 2.82 3.18
2.95 2.37 3.07 3.64
2.95 2.37 3.07 3.64
2.71 2.18 3.25 3.93
2.67 2.14 3.28 4.01
2.69 2.10 3.33 4.31
4.63 3.98 2.54 2.83 10.42
3.90 3.50 2.77 3.24
3.90 3.50 2.77 3.24
3.40 3.13 2.93 3.51
3.40 3.13 2.93 3.51
t
t
t
ZL
ZL
ZL
Table 2-7 on page 2-7
Table 2-7 on page 2-7
t
t
t
ZH
ZH
ZH
t
t
t
LZ
LZ
LZ
IGLOO Low Power Flash FPGAs
t
t
t
for derating values.
HZ
HZ
HZ
9.69
9.54
9.45
9.17
8.73
8.73
8.50
8.45
8.47
9.69
9.69
9.19
9.19
t
t
t
ZLS
ZLS
ZLS
for derating values.
for derating values.
9.72
9.72
9.32
9.23
9.24
8.54
8.15
8.15
7.97
7.93
7.89
9.76
9.29
9.29
8.91
8.91
t
t
t
ZHS
ZHS
ZHS
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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